mirror of https://github.com/PCSX2/pcsx2.git
Refactor some Sif code.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2472 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42
parent
14ebc021ad
commit
124f91920e
223
pcsx2/Sif.cpp
223
pcsx2/Sif.cpp
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@ -18,11 +18,9 @@
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#define _PC_ // disables MIPS opcode macros.
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#include "IopCommon.h"
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#include "Sif.h"
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DMACh *sif0ch, *sif1ch, *sif2ch;
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static _sif sif0, sif1;
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bool eesifbusy[2] = { false, false };
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@ -36,81 +34,7 @@ void sifInit()
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memzero(iopsifbusy);
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}
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__forceinline void SIF0Dma()
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{
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tDMA_TAG *ptag;
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bool done = false;
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int cycles = 0, psxCycles = 0;
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SIF_LOG("SIF0 DMA start...");
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do
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{
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if (iopsifbusy[0]) // If EE SIF0 is enabled
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{
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if (sif0.counter == 0) // If there's no more to transfer
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{
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// What this is supposed to do is stop DMA if it is the end of a chain, an interrupt is called, or in normal mode.
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// It currently doesn't check for normal mode.
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//
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// The old code for this was:
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// if (sif0.sifData.data & 0xC0000000)
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// which checks if the tag type is refe or end, or if the irq flag is set.
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// If the tag is refe or end, sif0.end gets set, so I'm replacing it with something easier to read: --arcum42
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if (/*(sif0dma->chcr.MOD == NORMAL_MODE) ||*/ sif0.end || DMA_TAG(sif0.sifData.data).IRQ)
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{
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SIF_LOG(" IOP SIF Stopped");
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// Stop & signal interrupts on IOP
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iopsifbusy[0] = false;
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords)
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// So when we're all done, the equation looks like thus:
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//PSX_INT(IopEvt_SIF0, ( ( psxCycles*BIAS ) / 4 ) / 8);
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PSX_INT(IopEvt_SIF0, psxCycles);
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sif0.sifData.data = 0;
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done = true;
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}
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else // Chain mode
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{
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// Process DMA tag at HW_DMA9_TADR
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sif0.sifData = *(sifData *)iopPhysMem(HW_DMA9_TADR);
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sif0.sifData.words = (sif0.sifData.words + 3) & 0xfffffffc; // Round up to nearest 4.
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//SIF0write((u32*)iopPhysMem(HW_DMA9_TADR + 8), 4);
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sif0.fifo.write((u32*)iopPhysMem(HW_DMA9_TADR + 8), 4);
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HW_DMA9_TADR += 16; ///HW_DMA9_MADR + 16 + sif0.sifData.words << 2;
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HW_DMA9_MADR = sif0.sifData.data & 0xFFFFFF;
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sif0.counter = sif0.sifData.words & 0xFFFFFF;
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SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.sifData.words, sif0.sifData.data);
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u32 tagId = DMA_TAG(sif0.sifData.data).ID;
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if ((tagId == TAG_REFE) || (tagId == TAG_END))
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SIF_LOG(" END");
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else
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SIF_LOG(" CNT %08X, %08X", sif0.sifData.data, sif0.sifData.words);
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done = false;
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}
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}
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else // There's some data ready to transfer into the fifo..
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{
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int wTransfer = min(sif0.counter, FIFO_SIF_W - sif0.fifo.size); // HW_DMA9_BCR >> 16;
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SIF_LOG("+++++++++++ %lX of %lX", wTransfer, sif0.counter /*(HW_DMA9_BCR >> 16)*/);
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sif0.fifo.write((u32*)iopPhysMem(HW_DMA9_MADR), wTransfer);
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HW_DMA9_MADR += wTransfer << 2;
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psxCycles += (wTransfer / 4) * BIAS; // fixme : should be / 16
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sif0.counter -= wTransfer;
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}
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}
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if (eesifbusy[0]) // If EE SIF enabled and there's something to transfer
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__forceinline void SIF0EEDma(int &cycles, int &psxCycles, bool &done)
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{
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int size = sif0dma->qwc;
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if (dmacRegs->ctrl.STS == STS_SIF0)
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@ -119,6 +43,7 @@ __forceinline void SIF0Dma()
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}
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if (size > 0) // If we're reading something continue to do so
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{
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tDMA_TAG *ptag;
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int readSize = min(size, (sif0.fifo.size >> 2));
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//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
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@ -182,46 +107,40 @@ __forceinline void SIF0Dma()
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break;
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}
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//sif0.chain = 1;
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done = false;
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}
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}
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}
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}
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while (!done);
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}
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__forceinline void SIF1Dma()
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{
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tDMA_TAG *ptag;
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bool done = FALSE;
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int cycles = 0, psxCycles = 0;
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do
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{
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if (eesifbusy[1]) // If EE SIF1 is enabled
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__forceinline void SIF1EEDma(int &cycles, int &psxCycles, bool &done)
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{
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if (dmacRegs->ctrl.STD == STD_SIF1)
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{
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SIF_LOG("SIF1 stall control"); // STD == fromSIF1
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}
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if (sif1dma->qwc == 0) // If there's no more to transfer
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// If there's no more to transfer.
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if (sif1dma->qwc == 0)
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{
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if ((sif1dma->chcr.MOD == NORMAL_MODE) || sif1.end) // If NORMAL mode or end of CHAIN then stop DMA
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// If NORMAL mode or end of CHAIN then stop DMA.
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if ((sif1dma->chcr.MOD == NORMAL_MODE) || sif1.end)
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{
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// Stop & signal interrupts on EE
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SIF_LOG("EE SIF1 End %x", sif1.end);
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eesifbusy[1] = false;
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done = true;
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// Voodoocycles : 4 cycles always, stops games from throwing double interrupts.
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// Edit: Ok, one game (Okami) wants bad timing aparently, so revert this until I know which values it likes.
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//CPU_INT(6, 4);
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CPU_INT(6, cycles*BIAS);
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//sif1.chain = 0;
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sif1.end = 0;
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}
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else // Chain mode
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else
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{
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// Chain mode
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tDMA_TAG *ptag;
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// Process DMA tag at sif1dma->tadr
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done = false;
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ptag = safeDmaGetAddr(sif1dma, sif1dma->tadr, DMAC_SIF1);
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@ -240,7 +159,6 @@ __forceinline void SIF1Dma()
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Console.WriteLn("SIF1 TIE");
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sif1.end = 1;
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}
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//sif1.chain = 1;
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switch (ptag->ID)
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{
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@ -282,18 +200,19 @@ __forceinline void SIF1Dma()
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}
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}
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}
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else // There's some data ready to transfer into the fifo..
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else
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{
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// There's some data ready to transfer into the fifo..
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int qwTransfer = sif1dma->qwc;
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tDMA_TAG *data;
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tDMA_TAG *pTag;
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data = safeDmaGetAddr(sif1dma, sif1dma->madr, DMAC_SIF1);
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if (data == NULL) return;
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pTag = safeDmaGetAddr(sif1dma, sif1dma->madr, DMAC_SIF1);
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if (pTag == NULL) return;
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if (qwTransfer > (FIFO_SIF_W - sif1.fifo.size) / 4) // Copy part of sif1dma into FIFO
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qwTransfer = (FIFO_SIF_W - sif1.fifo.size) / 4;
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sif1.fifo.write((u32*)data, qwTransfer << 2);
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sif1.fifo.write((u32*)pTag, qwTransfer << 2);
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sif1dma->madr += qwTransfer << 4;
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cycles += qwTransfer; // fixme : BIAS is factored in above
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@ -301,7 +220,69 @@ __forceinline void SIF1Dma()
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}
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}
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if (iopsifbusy[1]) // If IOP SIF enabled and there's something to transfer
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__forceinline void SIF0IOPDma(int &cycles, int &psxCycles, bool &done)
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{
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if (sif0.counter == 0) // If there's no more to transfer
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{
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// What this is supposed to do is stop DMA if it is the end of a chain, an interrupt is called, or in normal mode.
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// It currently doesn't check for normal mode.
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//
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// The old code for this was:
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// if (sif0.sifData.data & 0xC0000000)
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// which checks if the tag type is refe or end, or if the irq flag is set.
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// If the tag is refe or end, sif0.end gets set, so I'm replacing it with something easier to read: --arcum42
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if (/*(sif0dma->chcr.MOD == NORMAL_MODE) ||*/ sif0.end || DMA_TAG(sif0.data.data).IRQ)
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{
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SIF_LOG(" IOP SIF Stopped");
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// Stop & signal interrupts on IOP
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iopsifbusy[0] = false;
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords)
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// So when we're all done, the equation looks like thus:
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//PSX_INT(IopEvt_SIF0, ( ( psxCycles*BIAS ) / 4 ) / 8);
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PSX_INT(IopEvt_SIF0, psxCycles);
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sif0.data.data = 0;
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done = true;
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}
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else // Chain mode
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{
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// Process DMA tag at HW_DMA9_TADR
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sif0.data = *(sifData *)iopPhysMem(HW_DMA9_TADR);
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sif0.data.words = (sif0.data.words + 3) & 0xfffffffc; // Round up to nearest 4.
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sif0.fifo.write((u32*)iopPhysMem(HW_DMA9_TADR + 8), 4);
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HW_DMA9_TADR += 16; ///HW_DMA9_MADR + 16 + sif0.sifData.words << 2;
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HW_DMA9_MADR = sif0.data.data & 0xFFFFFF;
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sif0.counter = sif0.data.words & 0xFFFFFF;
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SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.data.words, sif0.data.data);
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u32 tagId = DMA_TAG(sif0.data.data).ID;
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if ((tagId == TAG_REFE) || (tagId == TAG_END))
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SIF_LOG(" END");
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else
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SIF_LOG(" CNT %08X, %08X", sif0.data.data, sif0.data.words);
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done = false;
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}
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}
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else // There's some data ready to transfer into the fifo..
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{
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int wTransfer = min(sif0.counter, FIFO_SIF_W - sif0.fifo.size); // HW_DMA9_BCR >> 16;
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SIF_LOG("+++++++++++ %lX of %lX", wTransfer, sif0.counter /*(HW_DMA9_BCR >> 16)*/);
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sif0.fifo.write((u32*)iopPhysMem(HW_DMA9_MADR), wTransfer);
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HW_DMA9_MADR += wTransfer << 2;
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psxCycles += (wTransfer / 4) * BIAS; // fixme : should be / 16
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sif0.counter -= wTransfer;
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}
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}
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__forceinline void SIF1IOPDma(int &cycles, int &psxCycles, bool &done)
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{
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int size = sif1.counter;
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@ -351,6 +332,48 @@ __forceinline void SIF1Dma()
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}
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}
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}
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__forceinline void SIF0Dma()
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{
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bool done = false;
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int cycles = 0, psxCycles = 0;
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SIF_LOG("SIF0 DMA start...");
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do
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{
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if (iopsifbusy[0])
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{
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// If EE SIF0 is enabled.
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SIF0IOPDma(cycles, psxCycles, done);
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}
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if (eesifbusy[0])
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{
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// If EE SIF enabled and there's something to transfer.
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SIF0EEDma(cycles, psxCycles, done);
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}
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}
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while (!done);
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}
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__forceinline void SIF1Dma()
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{
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bool done = false;
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int cycles = 0, psxCycles = 0;
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do
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{
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if (eesifbusy[1])
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{
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// If EE SIF1 is enabled.
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SIF1EEDma(cycles, psxCycles, done);
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}
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if (iopsifbusy[1])
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{
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// If IOP SIF enabled and there's something to transfer.
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SIF1IOPDma(cycles, psxCycles, done);
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}
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}
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while (!done);
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}
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@ -67,7 +67,7 @@ struct _sif
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s32 end;
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s32 tagMode;
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s32 counter;
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struct sifData sifData;
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struct sifData data;
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};
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extern DMACh *sif0ch, *sif1ch, *sif2ch;
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