debugger: initialized member

CID 147003
CID 147004
This commit is contained in:
Gregory Hainaut 2016-03-28 16:08:42 +02:00
parent 791a0ce702
commit 0fb249284f
3 changed files with 14 additions and 11 deletions

View File

@ -108,12 +108,13 @@ private:
class DisassemblyMacro: public DisassemblyEntry class DisassemblyMacro: public DisassemblyEntry
{ {
public: public:
DisassemblyMacro(DebugInterface* _cpu, u32 _address): cpu(_cpu), address(_address) { }; DisassemblyMacro(DebugInterface* _cpu, u32 _address):
cpu(_cpu), type(MACRO_LI), name(), immediate(0), address(_address), numOpcodes(0), rt(0), dataSize(0) { };
virtual ~DisassemblyMacro() { }; virtual ~DisassemblyMacro() { };
void setMacroLi(u32 _immediate, u8 _rt); void setMacroLi(u32 _immediate, u8 _rt);
void setMacroMemory(std::string _name, u32 _immediate, u8 _rt, int _dataSize); void setMacroMemory(std::string _name, u32 _immediate, u8 _rt, int _dataSize);
virtual void recheck() { }; virtual void recheck() { };
virtual int getNumLines() { return 1; }; virtual int getNumLines() { return 1; };
virtual int getLineNum(u32 address, bool findStart) { return 0; }; virtual int getLineNum(u32 address, bool findStart) { return 0; };
@ -122,7 +123,7 @@ public:
virtual bool disassemble(u32 address, DisassemblyLineInfo& dest, bool insertSymbols) ; virtual bool disassemble(u32 address, DisassemblyLineInfo& dest, bool insertSymbols) ;
private: private:
enum MacroType { MACRO_LI, MACRO_MEMORYIMM }; enum MacroType { MACRO_LI, MACRO_MEMORYIMM };
DebugInterface* cpu; DebugInterface* cpu;
MacroType type; MacroType type;
std::string name; std::string name;
@ -139,7 +140,7 @@ class DisassemblyData: public DisassemblyEntry
public: public:
DisassemblyData(DebugInterface* _cpu, u32 _address, u32 _size, DataType _type); DisassemblyData(DebugInterface* _cpu, u32 _address, u32 _size, DataType _type);
virtual ~DisassemblyData() { }; virtual ~DisassemblyData() { };
virtual void recheck(); virtual void recheck();
virtual int getNumLines() { return (int)lines.size(); }; virtual int getNumLines() { return (int)lines.size(); };
virtual int getLineNum(u32 address, bool findStart); virtual int getLineNum(u32 address, bool findStart);
@ -155,7 +156,7 @@ private:
u32 size; u32 size;
int lineNum; int lineNum;
}; };
DebugInterface* cpu; DebugInterface* cpu;
u32 address; u32 address;
u32 size; u32 size;
@ -170,7 +171,7 @@ class DisassemblyComment: public DisassemblyEntry
public: public:
DisassemblyComment(DebugInterface* _cpu, u32 _address, u32 _size, std::string name, std::string param); DisassemblyComment(DebugInterface* _cpu, u32 _address, u32 _size, std::string name, std::string param);
virtual ~DisassemblyComment() { }; virtual ~DisassemblyComment() { };
virtual void recheck() { }; virtual void recheck() { };
virtual int getNumLines() { return 1; }; virtual int getNumLines() { return 1; };
virtual int getLineNum(u32 address, bool findStart) { return 0; }; virtual int getLineNum(u32 address, bool findStart) { return 0; };

View File

@ -367,9 +367,11 @@ bool MipsCheckImmediate(const char* Source, DebugInterface* cpu, int& dest, int&
return true; return true;
} }
CMipsInstruction::CMipsInstruction(DebugInterface* cpu) CMipsInstruction::CMipsInstruction(DebugInterface* cpu) :
Opcode(), NoCheckError(false), Loaded(false), RamPos(0),
registers(), immediateType(MIPS_NOIMMEDIATE), immediate(),
vfpuSize(0), encoding(0), error()
{ {
Loaded = false;
this->cpu = cpu; this->cpu = cpu;
} }

View File

@ -43,11 +43,11 @@ struct MipsOpcodeRegisters {
MipsRegisterInfo grs; // general source reg MipsRegisterInfo grs; // general source reg
MipsRegisterInfo grt; // general target reg MipsRegisterInfo grt; // general target reg
MipsRegisterInfo grd; // general dest reg MipsRegisterInfo grd; // general dest reg
MipsRegisterInfo frs; // float source reg MipsRegisterInfo frs; // float source reg
MipsRegisterInfo frt; // float target reg MipsRegisterInfo frt; // float target reg
MipsRegisterInfo frd; // float dest reg MipsRegisterInfo frd; // float dest reg
MipsRegisterInfo ps2vrs; // ps2 vector source reg MipsRegisterInfo ps2vrs; // ps2 vector source reg
MipsRegisterInfo ps2vrt; // ps2 vector target reg MipsRegisterInfo ps2vrt; // ps2 vector target reg
MipsRegisterInfo ps2vrd; // ps2 vector dest reg MipsRegisterInfo ps2vrd; // ps2 vector dest reg