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pcsx2
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Chcr is a non-pod type. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2891 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2010-04-24 20:14:09 +00:00
parent 662d589217
commit 0f661e8f47
6 changed files with 9 additions and 9 deletions
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2
pcsx2/Gif.cpp
View File

@ -354,7 +354,7 @@ void dmaGIF()
//Halflife sets a QWC amount in chain mode, no tadr set.
if (gif->qwc > 0) gspath3done = true;
if(gif->chcr.MOD == CHAIN_MODE && gif->qwc > 0) DevCon.Warning("GIF QWC on Chain CHCR = %x", gif->chcr);
if(gif->chcr.MOD == CHAIN_MODE && gif->qwc > 0) DevCon.Warning(L"GIF QWC on Chain " + gif->chcr.desc());
GIFdma();
}

4
pcsx2/SPR.cpp
View File

@ -269,7 +269,7 @@ void dmaSPR0() // fromSPR
CPU_INT(DMAC_FROM_SPR, /*ptag[0].QWC / BIAS*/ 4 );
return;
}
if(spr0->chcr.MOD == CHAIN_MODE && spr0->qwc > 0) DevCon.Warning("SPR0 QWC on Chain CHCR = %x", spr0->chcr);
if(spr0->chcr.MOD == CHAIN_MODE && spr0->qwc > 0) DevCon.Warning(L"SPR0 QWC on Chain " + spr0->chcr.desc());
// COMPLETE HACK!!! For now at least.. FFX Videos dont rely on interrupts or reading DMA values
// It merely assumes that the last one has finished then starts another one (broke with the DMA fix)
// This "shouldn't" cause any problems as SPR is generally faster than the other DMAS anyway. (Refraction)
@ -417,7 +417,7 @@ void dmaSPR1() // toSPR
CPU_INT(DMAC_TO_SPR, /*ptag[0].QWC / BIAS*/ 4 );
return;
}
if(spr1->chcr.MOD == CHAIN_MODE && spr1->qwc > 0) DevCon.Warning("SPR1 QWC on Chain CHCR = %x", spr1->chcr);
if(spr1->chcr.MOD == CHAIN_MODE && spr1->qwc > 0) DevCon.Warning(L"SPR1 QWC on Chain " + spr1->chcr.desc());
// COMPLETE HACK!!! For now at least.. FFX Videos dont rely on interrupts or reading DMA values
// It merely assumes that the last one has finished then starts another one (broke with the DMA fix)
// This "shouldn't" cause any problems as SPR is generally faster than the other DMAS anyway. (Refraction)

2
pcsx2/Sif0.cpp
View File

@ -312,7 +312,7 @@ __forceinline void dmaSIF0()
SIF_LOG("warning, sif0.fifoReadPos != sif0.fifoWritePos");
}
if(sif0dma->chcr.MOD == CHAIN_MODE && sif0dma->qwc > 0) DevCon.Warning("SIF0 QWC on Chain CHCR = %x", sif0dma->chcr);
if(sif0dma->chcr.MOD == CHAIN_MODE && sif0dma->qwc > 0) DevCon.Warning(L"SIF0 QWC on Chain CHCR " + sif0dma->chcr.desc());
psHu32(SBUS_F240) |= 0x2000;
sif0.ee.busy = true;

2
pcsx2/Sif1.cpp
View File

@ -309,7 +309,7 @@ __forceinline void dmaSIF1()
SIF_LOG("warning, sif1.fifoReadPos != sif1.fifoWritePos");
}
if(sif1dma->chcr.MOD == CHAIN_MODE && sif1dma->qwc > 0) DevCon.Warning("SIF1 QWC on Chain CHCR = %x", sif1dma->chcr);
if(sif1dma->chcr.MOD == CHAIN_MODE && sif1dma->qwc > 0) DevCon.Warning(L"SIF1 QWC on Chain CHCR " + sif1dma->chcr.desc());
psHu32(SBUS_F240) |= 0x4000;
sif1.ee.busy = true;

4
pcsx2/Vif0_Dma.cpp
View File

@ -202,7 +202,7 @@ void dmaVIF0()
if ((vif0ch->chcr.MOD == NORMAL_MODE) || vif0ch->qwc > 0) // Normal Mode
{
vif0.dmamode = VIF_NORMAL_TO_MEM_MODE;
if(vif0ch->chcr.MOD == CHAIN_MODE && vif0ch->qwc > 0) DevCon.Warning("VIF0 QWC on Chain CHCR = %x", vif0ch->chcr);
if(vif0ch->chcr.MOD == CHAIN_MODE && vif0ch->qwc > 0) DevCon.Warning(L"VIF0 QWC on Chain CHCR " + vif0ch->chcr.desc());
}
else
{
@ -217,4 +217,4 @@ void dmaVIF0()
// Chain Mode
vif0.done = false;
vif0Interrupt();
}
}

4
pcsx2/Vif1_Dma.cpp
View File

@ -333,7 +333,7 @@ void dmaVIF1()
else
vif1.dmamode = VIF_NORMAL_TO_MEM_MODE;
if(vif1ch->chcr.MOD == CHAIN_MODE && vif1ch->qwc > 0) DevCon.Warning("VIF1 QWC on Chain CHCR = %x", vif1ch->chcr);
if(vif1ch->chcr.MOD == CHAIN_MODE && vif1ch->qwc > 0) DevCon.Warning(L"VIF1 QWC on Chain CHCR " + vif1ch->chcr.desc());
}
else
{
@ -344,4 +344,4 @@ void dmaVIF1()
// Chain Mode
vif1Interrupt();
}
}