mirror of https://github.com/PCSX2/pcsx2.git
parent
3269c58c8d
commit
0f1cbe7410
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@ -55,7 +55,7 @@ static void TestClearVUs(u32 madr, u32 qwc, bool isWrite)
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}
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}
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else if (madr >= 0x11004000 && madr < 0x11008000)
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else if (madr >= 0x11004000 && madr < 0x11008000)
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{
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{
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//SPR trying to write to to VU0 Mem mirror address.
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// SPR trying to write to to VU0 Mem mirror address.
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if(((madr & 0xff0) + (qwc * 16)) > 0x1000)
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if(((madr & 0xff0) + (qwc * 16)) > 0x1000)
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{
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{
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DevCon.Warning("Warning! SPR%d Crossing in to VU0 Mem Mirror address! Start MADR = %x, End MADR = %x", isWrite ? 0 : 1, madr, madr + (qwc * 16));
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DevCon.Warning("Warning! SPR%d Crossing in to VU0 Mem Mirror address! Start MADR = %x, End MADR = %x", isWrite ? 0 : 1, madr, madr + (qwc * 16));
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@ -123,12 +123,12 @@ int _SPR0chain()
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else
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else
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{
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{
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//Taking an arbitary small value for games which like to check the QWC/MADR instead of STR, so get most of
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// Taking an arbitary small value for games which like to check the QWC/MADR instead of STR, so get most of
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//the cycle delay out of the way before the end.
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// the cycle delay out of the way before the end.
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partialqwc = spr0ch.qwc;
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partialqwc = spr0ch.qwc;
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memcpy_from_spr((u8*)pMem, spr0ch.sadr, partialqwc*16);
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memcpy_from_spr((u8*)pMem, spr0ch.sadr, partialqwc*16);
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// clear VU mem also!
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// Clear VU mem also!
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TestClearVUs(spr0ch.madr, partialqwc, true);
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TestClearVUs(spr0ch.madr, partialqwc, true);
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spr0ch.madr += partialqwc << 4;
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spr0ch.madr += partialqwc << 4;
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@ -140,7 +140,7 @@ int _SPR0chain()
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return (partialqwc); // bus is 1/2 the ee speed
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return (partialqwc); // Bus is 1/2 the ee speed
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}
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}
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__fi void SPR0chain()
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__fi void SPR0chain()
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@ -179,7 +179,7 @@ void _SPR0interleave()
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case NO_MFD:
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case NO_MFD:
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case MFD_RESERVED:
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case MFD_RESERVED:
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// clear VU mem also!
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// Clear VU mem also!
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TestClearVUs(spr0ch.madr, spr0ch.qwc, true);
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TestClearVUs(spr0ch.madr, spr0ch.qwc, true);
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memcpy_from_spr((u8*)pMem, spr0ch.sadr, spr0ch.qwc*16);
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memcpy_from_spr((u8*)pMem, spr0ch.sadr, spr0ch.qwc*16);
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break;
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break;
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@ -204,7 +204,7 @@ static __fi void _dmaSPR0()
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{
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{
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case NORMAL_MODE:
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case NORMAL_MODE:
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{
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{
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if (dmacRegs.ctrl.STS == STS_fromSPR) // STS == fromSPR
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if (dmacRegs.ctrl.STS == STS_fromSPR) // STS == fromSPR
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{
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{
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DevCon.Warning("SPR stall control Normal not implemented");
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DevCon.Warning("SPR stall control Normal not implemented");
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}
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}
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@ -229,12 +229,12 @@ static __fi void _dmaSPR0()
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spr0ch.unsafeTransfer(ptag);
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spr0ch.unsafeTransfer(ptag);
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spr0ch.madr = ptag[1]._u32; //MADR = ADDR field + SPR
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spr0ch.madr = ptag[1]._u32; // MADR = ADDR field + SPR
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SPR_LOG("spr0 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
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SPR_LOG("spr0 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
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ptag[1]._u32, ptag[0]._u32, spr0ch.qwc, ptag->ID, spr0ch.madr, spr0ch.sadr);
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ptag[1]._u32, ptag[0]._u32, spr0ch.qwc, ptag->ID, spr0ch.madr, spr0ch.sadr);
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if (dmacRegs.ctrl.STS == STS_fromSPR) // STS == fromSPR
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if (dmacRegs.ctrl.STS == STS_fromSPR) // STS == fromSPR
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{
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{
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Console.WriteLn("SPR stall control");
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Console.WriteLn("SPR stall control");
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}
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}
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@ -242,7 +242,7 @@ static __fi void _dmaSPR0()
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switch (ptag->ID)
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switch (ptag->ID)
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{
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{
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case TAG_CNTS: // CNTS - Transfer QWC following the tag (Stall Control)
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case TAG_CNTS: // CNTS - Transfer QWC following the tag (Stall Control)
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if (dmacRegs.ctrl.STS == STS_fromSPR) dmacRegs.stadr.ADDR = spr0ch.madr + (spr0ch.qwc * 16); //Copy MADR to DMAC_STADR stall addr register
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if (dmacRegs.ctrl.STS == STS_fromSPR) dmacRegs.stadr.ADDR = spr0ch.madr + (spr0ch.qwc * 16); // Copy MADR to DMAC_STADR stall addr register
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break;
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break;
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case TAG_CNT: // CNT - Transfer QWC following the tag.
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case TAG_CNT: // CNT - Transfer QWC following the tag.
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@ -256,7 +256,7 @@ static __fi void _dmaSPR0()
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SPR0chain();
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SPR0chain();
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if (spr0ch.chcr.TIE && ptag->IRQ) //Check TIE bit of CHCR and IRQ bit of tag
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if (spr0ch.chcr.TIE && ptag->IRQ) // Check TIE bit of CHCR and IRQ bit of tag
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{
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{
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//Console.WriteLn("SPR0 TIE");
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//Console.WriteLn("SPR0 TIE");
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done = true;
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done = true;
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@ -288,8 +288,8 @@ void SPRFROMinterrupt()
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{
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{
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_dmaSPR0();
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_dmaSPR0();
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//the qwc check is simply because having data still to transfer from the packet can freak games out if they do a d.tadr == s.madr check
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// The qwc check is simply because having data still to transfer from the packet can freak games out if they do a d.tadr == s.madr check
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//and there is still data to come over (FF12 ingame menu)
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// and there is still data to come over (FF12 ingame menu)
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if(mfifotransferred != 0 && spr0ch.qwc == 0)
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if(mfifotransferred != 0 && spr0ch.qwc == 0)
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{
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{
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switch (dmacRegs.ctrl.MFD)
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switch (dmacRegs.ctrl.MFD)
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@ -330,8 +330,8 @@ void dmaSPR0() // fromSPR
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if(spr0ch.chcr.MOD == CHAIN_MODE && spr0ch.qwc > 0)
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if(spr0ch.chcr.MOD == CHAIN_MODE && spr0ch.qwc > 0)
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{
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{
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//DevCon.Warning(L"SPR0 QWC on Chain " + spr0ch.chcr.desc());
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//DevCon.Warning(L"SPR0 QWC on Chain " + spr0ch.chcr.desc());
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if (spr0ch.chcr.tag().ID == TAG_END) // but not TAG_REFE?
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if (spr0ch.chcr.tag().ID == TAG_END) // But not TAG_REFE?
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{ // Correct not REFE, Destination Chain doesnt have REFE!
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{ // correct not REFE, Destination Chain doesnt have REFE!
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spr0finished = true;
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spr0finished = true;
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}
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}
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}
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}
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@ -362,8 +362,8 @@ int _SPR1chain()
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pMem = SPRdmaGetAddr(spr1ch.madr, false);
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pMem = SPRdmaGetAddr(spr1ch.madr, false);
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if (pMem == NULL) return -1;
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if (pMem == NULL) return -1;
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int partialqwc = 0;
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int partialqwc = 0;
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//Taking an arbitary small value for games which like to check the QWC/MADR instead of STR, so get most of
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// Taking an arbitary small value for games which like to check the QWC/MADR instead of STR, so get most of
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//the cycle delay out of the way before the end.
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// the cycle delay out of the way before the end.
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partialqwc = spr1ch.qwc;
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partialqwc = spr1ch.qwc;
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SPR1transfer(pMem, partialqwc);
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SPR1transfer(pMem, partialqwc);
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@ -441,7 +441,7 @@ void _dmaSPR1() // toSPR work function
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}
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}
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// Chain Mode
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// Chain Mode
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ptag = SPRdmaGetAddr(spr1ch.tadr, false); //Set memory pointer to TADR
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ptag = SPRdmaGetAddr(spr1ch.tadr, false); // Set memory pointer to TADR
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if (!spr1ch.transfer("SPR1 Tag", ptag))
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if (!spr1ch.transfer("SPR1 Tag", ptag))
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{
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{
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@ -449,22 +449,22 @@ void _dmaSPR1() // toSPR work function
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spr1finished = done;
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spr1finished = done;
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}
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}
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spr1ch.madr = ptag[1]._u32; //MADR = ADDR field + SPR
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spr1ch.madr = ptag[1]._u32; // MADR = ADDR field + SPR
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// Transfer dma tag if tte is set
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// Transfer dma tag if tte is set
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if (spr1ch.chcr.TTE)
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if (spr1ch.chcr.TTE)
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{
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{
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SPR_LOG("SPR TTE: %x_%x\n", ptag[3]._u32, ptag[2]._u32);
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SPR_LOG("SPR TTE: %x_%x\n", ptag[3]._u32, ptag[2]._u32);
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SPR1transfer(ptag, 1); //Transfer Tag
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SPR1transfer(ptag, 1); // Transfer Tag
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}
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}
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SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx taddr=%lx saddr=%lx",
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SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx taddr=%lx saddr=%lx",
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ptag[1]._u32, ptag[0]._u32, spr1ch.qwc, ptag->ID, spr1ch.madr, spr1ch.tadr, spr1ch.sadr);
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ptag[1]._u32, ptag[0]._u32, spr1ch.qwc, ptag->ID, spr1ch.madr, spr1ch.tadr, spr1ch.sadr);
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done = hwDmacSrcChain(spr1ch, ptag->ID);
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done = hwDmacSrcChain(spr1ch, ptag->ID);
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SPR1chain(); //Transfers the data set by the switch
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SPR1chain(); // Transfers the data set by the switch
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if (spr1ch.chcr.TIE && ptag->IRQ) //Check TIE bit of CHCR and IRQ bit of tag
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if (spr1ch.chcr.TIE && ptag->IRQ) // Check TIE bit of CHCR and IRQ bit of tag
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{
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{
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SPR_LOG("dmaIrq Set");
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SPR_LOG("dmaIrq Set");
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@ -492,7 +492,7 @@ void dmaSPR1() // toSPR
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spr1ch.chcr._u32, spr1ch.madr, spr1ch.qwc,
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spr1ch.chcr._u32, spr1ch.madr, spr1ch.qwc,
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spr1ch.tadr, spr1ch.sadr);
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spr1ch.tadr, spr1ch.sadr);
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spr1finished = false; //Init
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spr1finished = false; // Init
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if(spr1ch.chcr.MOD == CHAIN_MODE && spr1ch.qwc > 0)
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if(spr1ch.chcr.MOD == CHAIN_MODE && spr1ch.qwc > 0)
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{
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{
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