From 0deb44c70dbf57a19ccf3c6d404a4bc9a0a0ddde Mon Sep 17 00:00:00 2001 From: cottonvibes Date: Mon, 16 Mar 2009 01:43:13 +0000 Subject: [PATCH] seems i had misunderstood ACC's pipeline rules. turns out there only needs to be 1 instance of it, so i had to fix all opcodes that use ACC. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@795 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/x86/microVU_Alloc.h | 34 +++--- pcsx2/x86/microVU_Alloc.inl | 214 ++++++++++++++---------------------- pcsx2/x86/microVU_Lower.inl | 20 ++-- pcsx2/x86/microVU_Misc.h | 17 +-- pcsx2/x86/microVU_Upper.inl | 152 +++++++------------------ 5 files changed, 158 insertions(+), 279 deletions(-) diff --git a/pcsx2/x86/microVU_Alloc.h b/pcsx2/x86/microVU_Alloc.h index 51ce87b21d..60611ebfbe 100644 --- a/pcsx2/x86/microVU_Alloc.h +++ b/pcsx2/x86/microVU_Alloc.h @@ -37,22 +37,28 @@ struct microAllocInfo { u8 q; u8 p; u8 r; - u16 info[pSize];// bit 0 = NOP? - // bit 1 = Used with bit 2 to make a 2-bit key for ACC write instance - // bit 2 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3) - // bit 3 = Used with bit 4 to make a 2-bit key for ACC read instance - // bit 4 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3) - // bit 5 = Write to Q1 or Q2? - // bit 6 = Read Q1 or Q2? - // bit 7 = Read/Write to P1 or P2? - // bit 8 = Update Mac Flags? - // bit 9 = Update Status Flags? + u32 info[pSize];// bit 00 = Lower Instruction is NOP + // bit 01 = Used with bit 2 to make a 2-bit key for ACC write instance + // bit 02 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3) + // bit 03 = Used with bit 4 to make a 2-bit key for ACC read instance + // bit 04 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3) + // bit 05 = Write to Q1 or Q2? + // bit 06 = Read Q1 or Q2? + // bit 07 = Read/Write to P1 or P2? + // bit 08 = Update Mac Flags? + // bit 09 = Update Status Flags? // bit 10 = Used with bit 11 to make a 2-bit key for mac flag instance - // bit 11 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3) + // bit 11 // bit 12 = Used with bit 13 to make a 2-bit key for status flag instance - // bit 13 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3) - // bit 14 = Read VI(Fs) from backup memory? - // bit 15 = Read VI(Ft) from backup memory? + // bit 13 + // bit 14 = Used with bit 15 to make a 2-bit key for clip flag instance + // bit 15 + // bit 16 = Used with bit 17 to make a 2-bit key for mac flag instance + // bit 17 + // bit 18 = Used with bit 19 to make a 2-bit key for status flag instance + // bit 19 + // bit 20 = Read VI(Fs) from backup memory? + // bit 21 = Read VI(Ft) from backup memory? u32 curPC; }; diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl index 6da7d4472e..ccd8a9221c 100644 --- a/pcsx2/x86/microVU_Alloc.inl +++ b/pcsx2/x86/microVU_Alloc.inl @@ -146,18 +146,18 @@ microVUt(void) mVUallocFMAC3b(int& Fd) { if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _xyzw_ACC); } \ else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ } - +/* #define getACC(reg) { \ reg = xmmACC0 + writeACC; \ if (_X_Y_Z_W != 15) { SSE_MOVAPS_XMM_to_XMM(reg, (xmmACC0 + prevACC)); } \ } - +*/ microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; - Fs = xmmFs; + ACC = xmmACC; + Fs = (_X_Y_Z_W == 15) ? xmmACC : xmmFs; Ft = xmmFt; - getACC(ACC); - if (_XYZW_SS && _X) { + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); if (_Ft_ == _Fs_) { Ft = Fs; } else { getReg6(Ft, _Ft_); } @@ -184,10 +184,10 @@ microVUt(void) mVUallocFMAC4b(int& ACC, int& Fs) { microVUt(void) mVUallocFMAC5a(int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; - Fs = xmmFs; + ACC = xmmACC; + Fs = (_X_Y_Z_W == 15) ? xmmACC : xmmFs; Ft = xmmFt; - getACC(ACC); - if (_XYZW_SS && _X) { + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); if ((_Ft_ == _Fs_) && _bc_x) { Ft = Fs; } else if (!_Ft_) { getZero3SS(Ft); } @@ -236,11 +236,11 @@ microVUt(void) mVUallocFMAC6b(int& Fd) { microVUt(void) mVUallocFMAC7a(int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; - Fs = xmmFs; + ACC = xmmACC; + Fs = (_X_Y_Z_W == 15) ? xmmACC : xmmFs; Ft = xmmFt; - getACC(ACC); getIreg(Ft); - if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); } else if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } } @@ -253,13 +253,13 @@ microVUt(void) mVUallocFMAC7b(int& ACC, int& Fs) { // FMAC8 - MADD FMAC Opcode Storing Result to Fd //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC8a(int& Fd, int&ACC, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC8a(int& Fd, int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; - ACC = xmmACC0 + readACC; - if (_XYZW_SS && _X) { + ACC = xmmACC; + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); if (_Ft_ == _Fs_) { Ft = Fs; } else { getReg6(Ft, _Ft_); } @@ -285,14 +285,14 @@ microVUt(void) mVUallocFMAC8b(int& Fd) { // FMAC9 - MSUB FMAC Opcode Storing Result to Fd //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC9a(int& Fd, int&ACC, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC9a(int& Fd, int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; ACC = xmmT1; - SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); - if (_XYZW_SS && _X) { + SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); if (_Ft_ == _Fs_) { Ft = Fs; } else { getReg6(Ft, _Ft_); } @@ -323,8 +323,8 @@ microVUt(void) mVUallocFMAC10a(int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; - ACC = xmmACC0 + readACC; - if (_XYZW_SS && _X) { + ACC = xmmACC; + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); if ( (_Ft_ == _Fs_) && _bc_x) { Ft = Fs; } else if (!_Ft_) { getZero3SS(Ft); } @@ -353,8 +353,8 @@ microVUt(void) mVUallocFMAC11a(int& Fd, int& ACC, int& Fs, int& Ft) { Ft = xmmFt; Fd = xmmT1; ACC = xmmT1; - SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); - if (_XYZW_SS && _X) { + SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); if ( (_Ft_ == _Fs_) && _bc_x) { Ft = Fs; } else if (!_Ft_) { getZero3SS(Ft); } @@ -377,14 +377,14 @@ microVUt(void) mVUallocFMAC11b(int& Fd) { // FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC12a(int& Fd, int&ACC, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC12a(int& Fd, int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; - ACC = xmmACC0 + readACC; + ACC = xmmACC; getIreg(Ft); - if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); } else if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } } @@ -397,15 +397,15 @@ microVUt(void) mVUallocFMAC12b(int& Fd) { // FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC13a(int& Fd, int&ACC, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC13a(int& Fd, int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; ACC = xmmT1; - SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); + SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); getIreg(Ft); - if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); } else if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } } @@ -415,16 +415,18 @@ microVUt(void) mVUallocFMAC13b(int& Fd) { } //------------------------------------------------------------------ -// FMAC14 - MADDA FMAC Opcode +// FMAC14 - MADDA/MSUBA FMAC Opcodes //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC14a(int& ACCw, int&ACCr, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC14a(int& ACCw, int& ACCr, int& Fs, int& Ft) { microVU* mVU = mVUx; - getACC(ACCw); - Fs = (_X_Y_Z_W == 15) ? ACCw : xmmFs; + Fs = xmmFs; Ft = xmmFt; - ACCr = xmmACC0 + readACC; - if (_XYZW_SS && _X) { + ACCw = xmmACC; + ACCr = ((_X_Y_Z_W == 15) || (_X_Y_Z_W == 8)) ? xmmACC : xmmT1; + SSE_MOVAPS_XMM_to_XMM(ACCr, xmmACC); + + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); if (_Ft_ == _Fs_) { Ft = Fs; } else { getReg6(Ft, _Ft_); } @@ -439,39 +441,25 @@ microVUt(void) mVUallocFMAC14a(int& ACCw, int&ACCr, int& Fs, int& Ft) { } } -microVUt(void) mVUallocFMAC14b(int& ACCw, int& Fs) { - microVU* mVU = mVUx; - if (CHECK_VU_OVERFLOW) mVUclamp1(Fs, xmmT1, _xyzw_ACC); - mVUmergeRegs(ACCw, Fs, _X_Y_Z_W); -} - -//------------------------------------------------------------------ -// FMAC15 - MSUBA FMAC Opcode -//------------------------------------------------------------------ - -microVUt(void) mVUallocFMAC15a(int& ACCw, int&ACCr, int& Fs, int& Ft) { - mVUallocFMAC14a(ACCw, ACCr, Fs, Ft); - SSE_MOVAPS_XMM_to_XMM(xmmT1, ACCr); - ACCr = xmmT1; -} - -microVUt(void) mVUallocFMAC15b(int& ACCw, int& ACCr) { +microVUt(void) mVUallocFMAC14b(int& ACCw, int& ACCr) { microVU* mVU = mVUx; if (CHECK_VU_OVERFLOW) mVUclamp1(ACCr, xmmFt, _xyzw_ACC); mVUmergeRegs(ACCw, ACCr, _X_Y_Z_W); } //------------------------------------------------------------------ -// FMAC16 - MADDA BC(xyzw) FMAC Opcode +// FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC16a(int& ACCw, int&ACCr, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC15a(int& ACCw, int& ACCr, int& Fs, int& Ft) { microVU* mVU = mVUx; - getACC(ACCw); - Fs = (_X_Y_Z_W == 15) ? ACCw : xmmFs; + Fs = xmmFs; Ft = xmmFt; - ACCr = xmmACC0 + readACC; - if (_XYZW_SS && _X) { + ACCw = xmmACC; + ACCr = ((_X_Y_Z_W == 15) || (_X_Y_Z_W == 8)) ? xmmACC : xmmT1; + SSE_MOVAPS_XMM_to_XMM(ACCr, xmmACC); + + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); if ((_Ft_ == _Fs_) && _bc_x) { Ft = Fs; } else if (!_Ft_) { getZero3SS(Ft); } @@ -486,22 +474,29 @@ microVUt(void) mVUallocFMAC16a(int& ACCw, int&ACCr, int& Fs, int& Ft) { } } -microVUt(void) mVUallocFMAC16b(int& ACCw, int& Fs) { - mVUallocFMAC14b(ACCw, Fs); +microVUt(void) mVUallocFMAC15b(int& ACCw, int& ACCr) { + mVUallocFMAC14b(ACCw, ACCr); } //------------------------------------------------------------------ -// FMAC17 - MSUBA BC(xyzw) FMAC Opcode +// FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC17a(int& ACCw, int&ACCr, int& Fs, int& Ft) { - mVUallocFMAC16a(ACCw, ACCr, Fs, Ft); - SSE_MOVAPS_XMM_to_XMM(xmmT1, ACCr); - ACCr = xmmT1; +microVUt(void) mVUallocFMAC16a(int& ACCw, int& ACCr, int& Fs, int& Ft) { + microVU* mVU = mVUx; + Fs = xmmFs; + Ft = xmmFt; + ACCw = xmmACC; + ACCr = ((_X_Y_Z_W == 15) || (_X_Y_Z_W == 8)) ? xmmACC : xmmT1; + SSE_MOVAPS_XMM_to_XMM(ACCr, xmmACC); + getIreg(Ft); + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); } + else if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } } -microVUt(void) mVUallocFMAC17b(int& ACCw, int& ACCr) { - mVUallocFMAC15b(ACCw, ACCr); +microVUt(void) mVUallocFMAC16b(int& ACCw, int& ACCr) { + mVUallocFMAC14b(ACCw, ACCr); } //------------------------------------------------------------------ @@ -512,7 +507,7 @@ microVUt(void) mVUallocFMAC18a(int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFt; - getACC(ACC); + ACC = xmmACC; if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } @@ -532,13 +527,13 @@ microVUt(void) mVUallocFMAC18b(int& ACC, int& Fs) { // FMAC19 - OPMULA FMAC Opcode //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC19a(int& Fd, int&ACC, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC19a(int& Fd, int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; ACC = xmmT1; - SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); + SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } @@ -554,40 +549,6 @@ microVUt(void) mVUallocFMAC19b(int& Fd) { mVUallocFMAC9b(Fd); } -//------------------------------------------------------------------ -// FMAC20 - MADDA FMAC Opcode (I Reg) -//------------------------------------------------------------------ - -microVUt(void) mVUallocFMAC20a(int& ACCw, int&ACCr, int& Fs, int& Ft) { - microVU* mVU = mVUx; - getACC(ACCw); - Fs = (_X_Y_Z_W == 15) ? ACCw : xmmFs; - Ft = xmmFt; - ACCr = xmmACC0 + readACC; - getIreg(Ft); - if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } - else if (!_Fs_) { getZero4(Fs); } - else { getReg4(Fs, _Fs_); } -} - -microVUt(void) mVUallocFMAC20b(int& ACCw, int& Fs) { - mVUallocFMAC14b(ACCw, Fs); -} - -//------------------------------------------------------------------ -// FMAC21 - MSUBA FMAC Opcode (I Reg) -//------------------------------------------------------------------ - -microVUt(void) mVUallocFMAC21a(int& ACCw, int&ACCr, int& Fs, int& Ft) { - mVUallocFMAC20a(ACCw, ACCr, Fs, Ft); - SSE_MOVAPS_XMM_to_XMM(xmmT1, ACCr); - ACCr = xmmT1; -} - -microVUt(void) mVUallocFMAC21b(int& ACCw, int& ACCr) { - mVUallocFMAC15b(ACCw, ACCr); -} - //------------------------------------------------------------------ // FMAC22 - Normal FMAC Opcodes (Q Reg) //------------------------------------------------------------------ @@ -616,11 +577,11 @@ microVUt(void) mVUallocFMAC22b(int& Fd) { microVUt(void) mVUallocFMAC23a(int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; - Fs = xmmFs; + ACC = xmmACC; + Fs = (_X_Y_Z_W == 15) ? xmmACC : xmmFs; Ft = xmmFt; - getACC(ACC); getQreg(Ft); - if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); } else if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } } @@ -633,14 +594,14 @@ microVUt(void) mVUallocFMAC23b(int& ACC, int& Fs) { // FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC24a(int& Fd, int&ACC, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC24a(int& Fd, int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; - ACC = xmmACC0 + readACC; + ACC = xmmACC; getQreg(Ft); - if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); } else if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } } @@ -653,15 +614,15 @@ microVUt(void) mVUallocFMAC24b(int& Fd) { // FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC25a(int& Fd, int&ACC, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC25a(int& Fd, int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; ACC = xmmT1; - SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC); + SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); getQreg(Ft); - if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); } else if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } } @@ -671,37 +632,24 @@ microVUt(void) mVUallocFMAC25b(int& Fd) { } //------------------------------------------------------------------ -// FMAC26 - MADDA FMAC Opcode (Q Reg) +// FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC26a(int& ACCw, int&ACCr, int& Fs, int& Ft) { +microVUt(void) mVUallocFMAC26a(int& ACCw, int& ACCr, int& Fs, int& Ft) { microVU* mVU = mVUx; - getACC(ACCw); - Fs = (_X_Y_Z_W == 15) ? ACCw : xmmFs; + Fs = xmmFs; Ft = xmmFt; - ACCr = xmmACC0 + readACC; + ACCw = xmmACC; + ACCr = ((_X_Y_Z_W == 15) || (_X_Y_Z_W == 8)) ? xmmACC : xmmT1; + SSE_MOVAPS_XMM_to_XMM(ACCr, xmmACC); getQreg(Ft); - if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); } + if (_X_Y_Z_W == 8) { getReg6(Fs, _Fs_); } else if (!_Fs_) { getZero4(Fs); } else { getReg4(Fs, _Fs_); } } -microVUt(void) mVUallocFMAC26b(int& ACCw, int& Fs) { - mVUallocFMAC14b(ACCw, Fs); -} - -//------------------------------------------------------------------ -// FMAC27 - MSUBA FMAC Opcode (Q Reg) -//------------------------------------------------------------------ - -microVUt(void) mVUallocFMAC27a(int& ACCw, int&ACCr, int& Fs, int& Ft) { - mVUallocFMAC26a(ACCw, ACCr, Fs, Ft); - SSE_MOVAPS_XMM_to_XMM(xmmT1, ACCr); - ACCr = xmmT1; -} - -microVUt(void) mVUallocFMAC27b(int& ACCw, int& ACCr) { - mVUallocFMAC15b(ACCw, ACCr); +microVUt(void) mVUallocFMAC26b(int& ACCw, int& ACCr) { + mVUallocFMAC14b(ACCw, ACCr); } //------------------------------------------------------------------ diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl index 1002a578f5..b2a3556385 100644 --- a/pcsx2/x86/microVU_Lower.inl +++ b/pcsx2/x86/microVU_Lower.inl @@ -405,10 +405,10 @@ microVUf(void) mVU_FCEQ() { microVU* mVU = mVUx; if (recPass == 0) {} else { - mVUallocCFLAGa(gprT2, fvcInstance); - XOR32RtoR(gprT1, gprT1); - CMP32ItoR(gprT2, _Imm24_); - SETNZ8R(gprT1); + mVUallocCFLAGa(gprT1, fvcInstance); + XOR32ItoR(gprT1, _Imm24_); + SUB32ItoR(gprT1, 1); + SHR32ItoR(gprT1, 31); mVUallocVIb(gprT1, 1); } } @@ -457,9 +457,9 @@ microVUf(void) mVU_FMEQ() { else { mVUallocMFLAGa(gprT1, fvmInstance); mVUallocVIa(gprT2, _Fs_); - CMP16RtoR(gprT1, gprT2); - SETE8R(gprT1); - AND16ItoR(gprT1, 0x1); + XOR32RtoR(gprT1, gprT2); + SUB32ItoR(gprT1, 1); + SHR32ItoR(gprT1, 31); mVUallocVIb(gprT1, _Ft_); } } @@ -488,9 +488,9 @@ microVUf(void) mVU_FSEQ() { if (recPass == 0) {} else { mVUallocSFLAGa(gprT1, fvsInstance); - CMP16ItoR(gprT1, _Imm12_); - SETE8R(gprT1); - AND16ItoR(gprT1, 0x1); + XOR16ItoR(gprT1, _Imm12_); + SUB16ItoR(gprT1, 1); + SHR16ItoR(gprT1, 15); mVUallocVIb(gprT1, _Ft_); } } diff --git a/pcsx2/x86/microVU_Misc.h b/pcsx2/x86/microVU_Misc.h index e28ec9c4e2..0c50cbb003 100644 --- a/pcsx2/x86/microVU_Misc.h +++ b/pcsx2/x86/microVU_Misc.h @@ -91,10 +91,10 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]); #define xmmT1 0 // Temp Reg #define xmmFs 1 // Holds the Value of Fs (writes back result Fd) #define xmmFt 2 // Holds the Value of Ft -#define xmmACC0 3 // Holds ACC Instance #0 -#define xmmACC1 4 // Holds ACC Instance #1 -#define xmmACC2 5 // Holds ACC Instance #2 -#define xmmACC3 6 // Holds ACC Instance #3 +#define xmmACC 3 // Holds ACC +#define xmmT2 4 // Temp Reg? +#define xmmT3 5 // Temp Reg? +#define xmmT4 6 // Temp Reg? #define xmmPQ 7 // Holds the Value and Backup Values of P and Q regs #define mmxVI1 0 // Holds VI 1 @@ -137,12 +137,13 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]); #define doStatus (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<9)) #define fmInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) >> 10) #define fsInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) >> 12) +#define fcInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<14)) >> 14) #define fpmInstance (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) >> 10) - 1) & 0x3) #define fpsInstance (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) >> 12) - 1) & 0x3) -#define fvmInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<14)) >> 14) -#define fvsInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<16)) >> 16) -#define fvcInstance 1//((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<14)) >> 14) -#define fcInstance 1//((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<14)) >> 14) +#define fvmInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<16)) >> 16) +#define fvsInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<18)) >> 18) +#define fvcInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<14)) >> 14) + //#define getFs (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<13)) //#define getFt (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<14)) diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl index 651ef92048..df8e7aa406 100644 --- a/pcsx2/x86/microVU_Upper.inl +++ b/pcsx2/x86/microVU_Upper.inl @@ -111,7 +111,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int ACC, Fs, Ft; \ mVUallocFMAC4a(ACC, Fs, Ft); \ - if (_XYZW_SS && _X) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ + if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ mVUallocFMAC4b(ACC, Fs); \ @@ -124,7 +124,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int ACC, Fs, Ft; \ mVUallocFMAC5a(ACC, Fs, Ft); \ - if (_XYZW_SS && _X) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ + if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ mVUallocFMAC5b(ACC, Fs); \ @@ -150,7 +150,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int ACC, Fs, Ft; \ mVUallocFMAC7a(ACC, Fs, Ft); \ - if (_XYZW_SS && _X) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ + if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ mVUallocFMAC7b(ACC, Fs); \ @@ -163,7 +163,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC8a(Fd, ACC, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \ } \ @@ -182,7 +182,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC9a(Fd, ACC, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \ } \ @@ -201,11 +201,11 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC10a(Fd, ACC, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \ } \ - else { \ + else { \ SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ @@ -220,7 +220,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC11a(Fd, ACC, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \ } \ @@ -239,7 +239,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC12a(Fd, ACC, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \ } \ @@ -258,7 +258,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC13a(Fd, ACC, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \ } \ @@ -270,33 +270,33 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC13b(Fd); \ } \ } -// FMAC14 - MADDA FMAC Opcode +// FMAC14 - MADDA/MSUBA FMAC Opcode #define mVU_FMAC14(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ else { \ int ACCw, ACCr, Fs, Ft; \ mVUallocFMAC14a(ACCw, ACCr, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##SS_XMM_to_XMM(Fs, ACCr); \ + SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ } \ else { \ SSE_MULPS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##PS_XMM_to_XMM(Fs, ACCr); \ + SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ - mVUallocFMAC14b(ACCw, Fs); \ + mVUupdateFlags(ACCr, Fs, Ft, _X_Y_Z_W, 0); \ + mVUallocFMAC14b(ACCw, ACCr); \ } \ } -// FMAC15 - MSUBA FMAC Opcode +// FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode #define mVU_FMAC15(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ else { \ int ACCw, ACCr, Fs, Ft; \ mVUallocFMAC15a(ACCw, ACCr, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ } \ @@ -308,33 +308,14 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC15b(ACCw, ACCr); \ } \ } -// FMAC16 - MADDA BC(xyzw) FMAC Opcode +// FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg) #define mVU_FMAC16(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ else { \ int ACCw, ACCr, Fs, Ft; \ mVUallocFMAC16a(ACCw, ACCr, Fs, Ft); \ - if (_XYZW_SS && _X) { \ - SSE_MULSS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##SS_XMM_to_XMM(Fs, ACCr); \ - } \ - else { \ - SSE_MULPS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##PS_XMM_to_XMM(Fs, ACCr); \ - } \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ - mVUallocFMAC16b(ACCw, Fs); \ - } \ -} -// FMAC17 - MSUBA BC(xyzw) FMAC Opcode -#define mVU_FMAC17(operation) { \ - microVU* mVU = mVUx; \ - if (recPass == 0) {} \ - else { \ - int ACCw, ACCr, Fs, Ft; \ - mVUallocFMAC17a(ACCw, ACCr, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ } \ @@ -343,7 +324,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ mVUupdateFlags(ACCr, Fs, Ft, _X_Y_Z_W, 0); \ - mVUallocFMAC17b(ACCw, ACCr); \ + mVUallocFMAC16b(ACCw, ACCr); \ } \ } // FMAC18 - OPMULA FMAC Opcode @@ -371,44 +352,6 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC19b(Fd); \ } \ } -// FMAC20 - MADDA FMAC Opcode (I Reg) -#define mVU_FMAC20(operation) { \ - microVU* mVU = mVUx; \ - if (recPass == 0) {} \ - else { \ - int ACCw, ACCr, Fs, Ft; \ - mVUallocFMAC20a(ACCw, ACCr, Fs, Ft); \ - if (_XYZW_SS && _X) { \ - SSE_MULSS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##SS_XMM_to_XMM(Fs, ACCr); \ - } \ - else { \ - SSE_MULPS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##PS_XMM_to_XMM(Fs, ACCr); \ - } \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ - mVUallocFMAC20b(ACCw, Fs); \ - } \ -} -// FMAC21 - MSUBA FMAC Opcode (I Reg) -#define mVU_FMAC21(operation) { \ - microVU* mVU = mVUx; \ - if (recPass == 0) {} \ - else { \ - int ACCw, ACCr, Fs, Ft; \ - mVUallocFMAC21a(ACCw, ACCr, Fs, Ft); \ - if (_XYZW_SS && _X) { \ - SSE_MULSS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ - } \ - else { \ - SSE_MULPS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ - } \ - mVUupdateFlags(ACCr, Fs, Ft, _X_Y_Z_W, 0); \ - mVUallocFMAC21b(ACCw, ACCr); \ - } \ -} // FMAC22 - Normal FMAC Opcodes (Q Reg) #define mVU_FMAC22(operation) { \ microVU* mVU = mVUx; \ @@ -429,7 +372,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int ACC, Fs, Ft; \ mVUallocFMAC23a(ACC, Fs, Ft); \ - if (_XYZW_SS && _X) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ + if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ mVUallocFMAC23b(ACC, Fs); \ @@ -442,7 +385,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC24a(Fd, ACC, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \ } \ @@ -461,7 +404,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC25a(Fd, ACC, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \ } \ @@ -473,33 +416,14 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX mVUallocFMAC25b(Fd); \ } \ } -// FMAC26 - MADDA FMAC Opcode (Q Reg) +// FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg) #define mVU_FMAC26(operation) { \ microVU* mVU = mVUx; \ if (recPass == 0) {} \ else { \ int ACCw, ACCr, Fs, Ft; \ mVUallocFMAC26a(ACCw, ACCr, Fs, Ft); \ - if (_XYZW_SS && _X) { \ - SSE_MULSS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##SS_XMM_to_XMM(Fs, ACCr); \ - } \ - else { \ - SSE_MULPS_XMM_to_XMM(Fs, Ft); \ - SSE_##operation##PS_XMM_to_XMM(Fs, ACCr); \ - } \ - mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ - mVUallocFMAC26b(ACCw, Fs); \ - } \ -} -// FMAC27 - MSUBA FMAC Opcode (Q Reg) -#define mVU_FMAC27(operation) { \ - microVU* mVU = mVUx; \ - if (recPass == 0) {} \ - else { \ - int ACCw, ACCr, Fs, Ft; \ - mVUallocFMAC27a(ACCw, ACCr, Fs, Ft); \ - if (_XYZW_SS && _X) { \ + if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ } \ @@ -508,7 +432,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ mVUupdateFlags(ACCr, Fs, Ft, _X_Y_Z_W, 0); \ - mVUallocFMAC27b(ACCw, ACCr); \ + mVUallocFMAC26b(ACCw, ACCr); \ } \ } @@ -576,12 +500,12 @@ microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD); } microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD); } microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD); } microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD); } -microVUf(void) mVU_MADDAi() { mVU_FMAC20(ADD); } +microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD); } microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD); } -microVUf(void) mVU_MADDAx() { mVU_FMAC16(ADD); } -microVUf(void) mVU_MADDAy() { mVU_FMAC16(ADD); } -microVUf(void) mVU_MADDAz() { mVU_FMAC16(ADD); } -microVUf(void) mVU_MADDAw() { mVU_FMAC16(ADD); } +microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD); } +microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD); } +microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD); } +microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD); } microVUf(void) mVU_MSUB() { mVU_FMAC9(SUB); } microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB); } microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB); } @@ -590,12 +514,12 @@ microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB); } microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB); } microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB); } microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB); } -microVUf(void) mVU_MSUBAi() { mVU_FMAC21(SUB); } -microVUf(void) mVU_MSUBAq() { mVU_FMAC27(SUB); } -microVUf(void) mVU_MSUBAx() { mVU_FMAC17(SUB); } -microVUf(void) mVU_MSUBAy() { mVU_FMAC17(SUB); } -microVUf(void) mVU_MSUBAz() { mVU_FMAC17(SUB); } -microVUf(void) mVU_MSUBAw() { mVU_FMAC17(SUB); } +microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB); } +microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB); } +microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB); } +microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB); } +microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB); } +microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB); } microVUf(void) mVU_MAX() { mVU_FMAC1(MAX); } microVUf(void) mVU_MAXi() { mVU_FMAC6(MAX); } microVUf(void) mVU_MAXx() { mVU_FMAC3(MAX); }