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Reverted most changes from r326, the excessive code will get used later. Also removed some dead code that's been in the eerec for ages. 

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@329 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
ramapcsx2 2008-11-15 12:59:39 +00:00 committed by Gregory Hainaut
parent 7fd2888335
commit 0cb03d20a7
3 changed files with 2 additions and 19 deletions
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4
pcsx2/Counters.c
View File

@ -78,9 +78,7 @@ static __forceinline void cpuRcntSet() {
// This must be done regardless of if the hblank/vblank counters updated since // This must be done regardless of if the hblank/vblank counters updated since
// cpuRegs.cycle changes, even if sCycle hasn't! // cpuRegs.cycle changes, even if sCycle hasn't!
//fixme : HBLANK_TIME_ and HRENDER_TIME_ are both SCANLINE_NTSC (or _PAL) / 2.. was that intended? (rama) u32 counter4CycleT = ( counters[4].mode == MODE_HBLANK ) ? HBLANK_TIME_ : HRENDER_TIME_;
//u32 counter4CycleT = ( counters[4].mode == MODE_HBLANK ) ? HBLANK_TIME_ : HRENDER_TIME_;
u32 counter4CycleT = HBLANK_TIME_;
u32 counter5CycleT = VSYNC_HALF_ - (cpuRegs.cycle - counters[5].sCycle); u32 counter5CycleT = VSYNC_HALF_ - (cpuRegs.cycle - counters[5].sCycle);
counter4CycleT -= (cpuRegs.cycle - counters[4].sCycle); counter4CycleT -= (cpuRegs.cycle - counters[4].sCycle);

4
pcsx2/Counters.h
View File

@ -36,8 +36,6 @@ typedef struct {
// NTSC Timing Information!!! (some scanline info is guessed) // NTSC Timing Information!!! (some scanline info is guessed)
//------------------------------------------------------------------ //------------------------------------------------------------------
#define SCANLINE_NTSC (u32)(PS2CLK / 15734.25)//18743 //when using 59.94005994 it rounds to 15734.27 :p (rama) #define SCANLINE_NTSC (u32)(PS2CLK / 15734.25)//18743 //when using 59.94005994 it rounds to 15734.27 :p (rama)
// fixme : Both, HRENDER_TIME_NTSC and HBLANK_TIME_NTSC the same?
// also see cpuRcntSet() and possibly hScanline() for this issue (rama)
#define HRENDER_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//15528 //time from hblank end to hblank start (PS2CLK / 18991.368423051722991900181367568) #define HRENDER_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//15528 //time from hblank end to hblank start (PS2CLK / 18991.368423051722991900181367568)
#define HBLANK_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//3215 //time from hblank start to hblank end (PS2CLK / 91738.91105912572817760653181028) #define HBLANK_TIME_NTSC (u32)(SCANLINE_NTSC / 2)//3215 //time from hblank start to hblank end (PS2CLK / 91738.91105912572817760653181028)
#define VSYNC_NTSC (u32)(PS2CLK / 59.94) //hz //59.94005994 is more precise #define VSYNC_NTSC (u32)(PS2CLK / 59.94) //hz //59.94005994 is more precise
@ -55,8 +53,6 @@ typedef struct {
// PAL Timing Information!!! (some scanline info is guessed) // PAL Timing Information!!! (some scanline info is guessed)
//------------------------------------------------------------------ //------------------------------------------------------------------
#define SCANLINE_PAL (u32)(PS2CLK / 15625)//18874 #define SCANLINE_PAL (u32)(PS2CLK / 15625)//18874
// fixme : Both, HRENDER_TIME_PAL and HBLANK_TIME_PAL the same?
// also see cpuRcntSet() and possibly hScanline() for this issue (rama)
#define HRENDER_TIME_PAL (u32)(SCANLINE_PAL / 2)//15335 //time from hblank end to hblank start #define HRENDER_TIME_PAL (u32)(SCANLINE_PAL / 2)//15335 //time from hblank end to hblank start
#define HBLANK_TIME_PAL (u32)(SCANLINE_PAL / 2)//3539 //time from hblank start to hblank end #define HBLANK_TIME_PAL (u32)(SCANLINE_PAL / 2)//3539 //time from hblank start to hblank end
#define VSYNC_PAL (u32)(PS2CLK / 50) //hz #define VSYNC_PAL (u32)(PS2CLK / 50) //hz

13
pcsx2/x86/ix86-32/iR5900-32.c
View File

@ -81,8 +81,7 @@ u32 g_EEFreezeRegs = 0; // if set, should freeze the regs
static BASEBLOCK* s_pCurBlock = NULL; static BASEBLOCK* s_pCurBlock = NULL;
static BASEBLOCKEX* s_pCurBlockEx = NULL; static BASEBLOCKEX* s_pCurBlockEx = NULL;
static BASEBLOCK* s_pDispatchBlock = NULL; static BASEBLOCK* s_pDispatchBlock = NULL;
static u32 s_nEndBlock = 0; // what pc the current block ends static u32 s_nEndBlock = 0; // what pc the current block ends
static u32 s_nHasDelay = 0;
static u32 s_nNextBlock = 0; // next free block in recBlocks static u32 s_nNextBlock = 0; // next free block in recBlocks
@ -2914,7 +2913,6 @@ void recRecompile( u32 startpc )
// go until the next branch // go until the next branch
i = startpc; i = startpc;
s_nEndBlock = 0xffffffff; s_nEndBlock = 0xffffffff;
s_nHasDelay = 0;
while(1) { while(1) {
BASEBLOCK* pblock = PC_GETBLOCK(i); BASEBLOCK* pblock = PC_GETBLOCK(i);
@ -2935,7 +2933,6 @@ void recRecompile( u32 startpc )
if( _Funct_ == 8 || _Funct_ == 9 ) { // JR, JALR if( _Funct_ == 8 || _Funct_ == 9 ) { // JR, JALR
s_nEndBlock = i + 8; s_nEndBlock = i + 8;
s_nHasDelay = 1;
goto StartRecomp; goto StartRecomp;
} }
@ -2944,8 +2941,6 @@ void recRecompile( u32 startpc )
if( _Rt_ < 4 || (_Rt_ >= 16 && _Rt_ < 20) ) { if( _Rt_ < 4 || (_Rt_ >= 16 && _Rt_ < 20) ) {
// branches // branches
if( _Rt_ == 2 || _Rt_ == 3 || _Rt_ == 18 || _Rt_ == 19 ) s_nHasDelay = 1;
else s_nHasDelay = 2;
branchTo = _Imm_ * 4 + i + 4; branchTo = _Imm_ * 4 + i + 4;
if( branchTo > startpc && branchTo < i ) s_nEndBlock = branchTo; if( branchTo > startpc && branchTo < i ) s_nEndBlock = branchTo;
@ -2958,7 +2953,6 @@ void recRecompile( u32 startpc )
case 2: // J case 2: // J
case 3: // JAL case 3: // JAL
s_nHasDelay = 1;
s_nEndBlock = i + 8; s_nEndBlock = i + 8;
goto StartRecomp; goto StartRecomp;
@ -2966,9 +2960,6 @@ void recRecompile( u32 startpc )
case 4: case 5: case 6: case 7: case 4: case 5: case 6: case 7:
case 20: case 21: case 22: case 23: case 20: case 21: case 22: case 23:
if( (cpuRegs.code >> 26) >= 20 ) s_nHasDelay = 1;
else s_nHasDelay = 2;
branchTo = _Imm_ * 4 + i + 4; branchTo = _Imm_ * 4 + i + 4;
if( branchTo > startpc && branchTo < i ) s_nEndBlock = branchTo; if( branchTo > startpc && branchTo < i ) s_nEndBlock = branchTo;
else s_nEndBlock = i+8; else s_nEndBlock = i+8;
@ -2989,8 +2980,6 @@ void recRecompile( u32 startpc )
if( _Rs_ == 8 ) { if( _Rs_ == 8 ) {
// BC1F, BC1T, BC1FL, BC1TL // BC1F, BC1T, BC1FL, BC1TL
// BC2F, BC2T, BC2FL, BC2TL // BC2F, BC2T, BC2FL, BC2TL
if( _Rt_ >= 2 ) s_nHasDelay = 1;
else s_nHasDelay = 2;
branchTo = _Imm_ * 4 + i + 4; branchTo = _Imm_ * 4 + i + 4;
if( branchTo > startpc && branchTo < i ) s_nEndBlock = branchTo; if( branchTo > startpc && branchTo < i ) s_nEndBlock = branchTo;