mirror of https://github.com/PCSX2/pcsx2.git
Minor iCore.c changes. A few if/else statements are now case statements, a few compiler warnings are taken care of, a few variables are no longer assigned inside if statements, etc...
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@337 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
arcum42
Gregory Hainaut
parent
d24add597e
commit
098e6b509b
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@ -108,17 +108,28 @@ void _initXMMregs() {
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__forceinline void* _XMMGetAddr(int type, int reg, VURegs *VU)
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{
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if (type == XMMTYPE_VFREG ) return (void*)VU_VFx_ADDR(reg);
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else if (type == XMMTYPE_ACC ) return (void*)VU_ACCx_ADDR;
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else if (type == XMMTYPE_GPRREG) {
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switch (type) {
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case XMMTYPE_VFREG:
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return (void*)VU_VFx_ADDR(reg);
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case XMMTYPE_ACC:
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return (void*)VU_ACCx_ADDR;
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case XMMTYPE_GPRREG:
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if( reg < 32 )
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assert( !(g_cpuHasConstReg & (1<<reg)) || (g_cpuFlushedConstReg & (1<<reg)) );
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return &cpuRegs.GPR.r[reg].UL[0];
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}
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else if (type == XMMTYPE_FPREG ) return &fpuRegs.fpr[reg];
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else if (type == XMMTYPE_FPACC ) return &fpuRegs.ACC.f;
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case XMMTYPE_FPREG:
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return &fpuRegs.fpr[reg];
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case XMMTYPE_FPACC:
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return &fpuRegs.ACC.f;
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default:
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assert(0);
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}
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return NULL;
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}
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@ -205,7 +216,9 @@ int _allocVFtoXMMreg(VURegs *VU, int xmmreg, int vfreg, int mode) {
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int readfromreg = -1;
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for (i=0; i<XMMREGS; i++) {
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if (xmmregs[i].inuse == 0 || xmmregs[i].type != XMMTYPE_VFREG || xmmregs[i].reg != vfreg || xmmregs[i].VU != XMM_CONV_VU(VU) ) continue;
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if ((xmmregs[i].inuse == 0) || (xmmregs[i].type != XMMTYPE_VFREG) ||
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(xmmregs[i].reg != vfreg) || (xmmregs[i].VU != XMM_CONV_VU(VU)))
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continue;
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if( xmmreg >= 0 ) {
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// requested specific reg, so return that instead
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@ -231,12 +244,10 @@ int _allocVFtoXMMreg(VURegs *VU, int xmmreg, int vfreg, int mode) {
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return i;
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}
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if (xmmreg == -1) {
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if (xmmreg == -1)
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xmmreg = _getFreeXMMreg();
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}
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else {
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else
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_freeXMMreg(xmmreg);
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}
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g_xmmtypes[xmmreg] = XMMT_FPS;
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xmmregs[xmmreg].inuse = 1;
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@ -259,7 +270,7 @@ int _checkXMMreg(int type, int reg, int mode)
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int i;
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for (i=0; i<XMMREGS; i++) {
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if (xmmregs[i].inuse && xmmregs[i].type == (type&0xff) && xmmregs[i].reg == reg ) {
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if (xmmregs[i].inuse && (xmmregs[i].type == (type&0xff)) && (xmmregs[i].reg == reg)) {
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if ( !(xmmregs[i].mode & MODE_READ) ) {
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if (mode & MODE_READ) {
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@ -315,12 +326,10 @@ int _allocACCtoXMMreg(VURegs *VU, int xmmreg, int mode) {
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return i;
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}
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if (xmmreg == -1) {
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if (xmmreg == -1)
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xmmreg = _getFreeXMMreg();
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}
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else {
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else
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_freeXMMreg(xmmreg);
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}
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g_xmmtypes[xmmreg] = XMMT_FPS;
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xmmregs[xmmreg].inuse = 1;
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@ -331,9 +340,12 @@ int _allocACCtoXMMreg(VURegs *VU, int xmmreg, int mode) {
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xmmregs[xmmreg].counter = g_xmmAllocCounter++;
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xmmregs[xmmreg].reg = 0;
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if (mode & MODE_READ) {
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if( readfromreg >= 0 ) SSE_MOVAPS_XMM_to_XMM(xmmreg, readfromreg);
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else SSE_MOVAPS_M128_to_XMM(xmmreg, VU_ACCx_ADDR);
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if (mode & MODE_READ)
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{
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if( readfromreg >= 0 )
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SSE_MOVAPS_XMM_to_XMM(xmmreg, readfromreg);
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else
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SSE_MOVAPS_M128_to_XMM(xmmreg, VU_ACCx_ADDR);
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}
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return xmmreg;
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@ -359,9 +371,7 @@ int _allocFPtoXMMreg(int xmmreg, int fpreg, int mode) {
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return i;
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}
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if (xmmreg == -1) {
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xmmreg = _getFreeXMMreg();
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}
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if (xmmreg == -1) xmmreg = _getFreeXMMreg();
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g_xmmtypes[xmmreg] = XMMT_FPS;
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xmmregs[xmmreg].inuse = 1;
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@ -371,9 +381,8 @@ int _allocFPtoXMMreg(int xmmreg, int fpreg, int mode) {
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xmmregs[xmmreg].needed = 1;
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xmmregs[xmmreg].counter = g_xmmAllocCounter++;
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if (mode & MODE_READ) {
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if (mode & MODE_READ)
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SSE_MOVSS_M32_to_XMM(xmmreg, (uptr)&fpuRegs.fpr[fpreg].f);
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}
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return xmmreg;
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}
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@ -382,7 +391,8 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
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{
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int i;
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for (i=0; i<XMMREGS; i++) {
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for (i=0; i<XMMREGS; i++)
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{
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if (xmmregs[i].inuse == 0) continue;
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if (xmmregs[i].type != XMMTYPE_GPRREG) continue;
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if (xmmregs[i].reg != gprreg) continue;
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@ -392,11 +402,14 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
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#endif
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g_xmmtypes[i] = XMMT_INT;
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if( !(xmmregs[i].mode & MODE_READ) && (mode&MODE_READ)) {
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if( gprreg == 0 ) {
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if (!(xmmregs[i].mode & MODE_READ) && (mode & MODE_READ))
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{
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if (gprreg == 0 )
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{
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SSEX_PXOR_XMM_to_XMM(i, i);
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}
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else {
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else
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{
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//assert( !(g_cpuHasConstReg & (1<<gprreg)) || (g_cpuFlushedConstReg & (1<<gprreg)) );
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_flushConstReg(gprreg);
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SSEX_MOVDQA_M128_to_XMM(i, (uptr)&cpuRegs.GPR.r[gprreg].UL[0]);
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@ -404,7 +417,8 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
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xmmregs[i].mode |= MODE_READ;
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}
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if( (mode & MODE_WRITE) && gprreg < 32 ) {
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if ((mode & MODE_WRITE) && (gprreg < 32))
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{
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g_cpuHasConstReg &= ~(1<<gprreg);
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//assert( !(g_cpuHasConstReg & (1<<gprreg)) );
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}
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@ -416,14 +430,14 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
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}
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// currently only gpr regs are const
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if( (mode & MODE_WRITE) && gprreg < 32 ) {
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// fixme - do we really need to execute this both here and in the loop?
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if ((mode & MODE_WRITE) && gprreg < 32)
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{
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//assert( !(g_cpuHasConstReg & (1<<gprreg)) );
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g_cpuHasConstReg &= ~(1<<gprreg);
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}
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if (xmmreg == -1) {
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xmmreg = _getFreeXMMreg();
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}
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if (xmmreg == -1) xmmreg = _getFreeXMMreg();
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g_xmmtypes[xmmreg] = XMMT_INT;
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xmmregs[xmmreg].inuse = 1;
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@ -433,28 +447,35 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
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xmmregs[xmmreg].needed = 1;
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xmmregs[xmmreg].counter = g_xmmAllocCounter++;
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if (mode & MODE_READ) {
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if( gprreg == 0 ) {
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if (mode & MODE_READ)
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{
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if (gprreg == 0 )
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{
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SSEX_PXOR_XMM_to_XMM(xmmreg, xmmreg);
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}
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else {
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else
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{
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// DOX86
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int mmxreg;
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if( (mode&MODE_READ) ) _flushConstReg(gprreg);
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if (mode & MODE_READ) _flushConstReg(gprreg);
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#ifndef __x86_64__
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if( (mmxreg = _checkMMXreg(MMX_GPR+gprreg, 0)) >= 0 ) {
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// transfer
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mmxreg = _checkMMXreg(MMX_GPR+gprreg, 0);
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if (mmxreg >= 0 )
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{
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// transfer
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SetMMXstate();
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SSE2_MOVQ2DQ_MM_to_XMM(xmmreg, mmxreg);
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SSE2_PUNPCKLQDQ_XMM_to_XMM(xmmreg, xmmreg);
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SSE2_PUNPCKHQDQ_M128_to_XMM(xmmreg, (u32)&cpuRegs.GPR.r[gprreg].UL[0]);
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if( mmxregs[mmxreg].mode & MODE_WRITE ) {
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if (mmxregs[mmxreg].mode & MODE_WRITE )
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{
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// instead of setting to write, just flush to mem
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if( !(mode & MODE_WRITE) ) {
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if (!(mode & MODE_WRITE))
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{
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SetMMXstate();
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MOVQRtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], mmxreg);
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}
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@ -465,14 +486,16 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
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mmxregs[mmxreg].inuse = 0;
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}
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#else
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if( (mmxreg = _checkX86reg(X86TYPE_GPR, gprreg, 0)) >= 0 ) {
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mmxreg = _checkX86reg(X86TYPE_GPR, gprreg, 0);
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if (mmxreg >= 0 )
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{
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SSE2_MOVQ_R_to_XMM(xmmreg, mmxreg);
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SSE_MOVHPS_M64_to_XMM(xmmreg, (uptr)&cpuRegs.GPR.r[gprreg].UL[0]);
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// read only, instead of setting to write, just flush to mem
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if( !(mode&MODE_WRITE) && (x86regs[mmxreg].mode & MODE_WRITE) ) {
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if (!(mode & MODE_WRITE) && (x86regs[mmxreg].mode & MODE_WRITE) )
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MOV64RtoM((uptr)&cpuRegs.GPR.r[gprreg].UL[0], mmxreg);
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}
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x86regs[mmxreg].inuse = 0;
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}
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@ -483,7 +506,8 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
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}
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}
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}
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else {
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else
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{
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#ifndef __x86_64__
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_deleteMMXreg(MMX_GPR+gprreg, 0);
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#else
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@ -625,34 +649,42 @@ void _deleteVFtoXMMreg(int reg, int vu, int flush)
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int i;
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VURegs *VU = vu ? &VU1 : &VU0;
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for (i=0; i<XMMREGS; i++) {
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if (xmmregs[i].inuse && xmmregs[i].type == XMMTYPE_VFREG && xmmregs[i].reg == reg && xmmregs[i].VU == vu) {
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for (i=0; i<XMMREGS; i++)
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{
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if (xmmregs[i].inuse && (xmmregs[i].type == XMMTYPE_VFREG) &&
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(xmmregs[i].reg == reg) && (xmmregs[i].VU == vu))
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{
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switch(flush) {
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case 0:
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_freeXMMreg(i);
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break;
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case 1:
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case 2:
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if( xmmregs[i].mode & MODE_WRITE ) {
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if( xmmregs[i].mode & MODE_WRITE )
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{
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assert( reg != 0 );
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if( xmmregs[i].mode & MODE_VUXYZ ) {
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if( xmmregs[i].mode & MODE_VUZ ) {
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if( xmmregs[i].mode & MODE_VUXYZ )
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{
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if( xmmregs[i].mode & MODE_VUZ )
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{
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// xyz, don't destroy w
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int t0reg;
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for(t0reg = 0; t0reg < XMMREGS; ++t0reg ) {
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if( !xmmregs[t0reg].inuse ) break;
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for (t0reg = 0; t0reg < XMMREGS; ++t0reg)
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{
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if (!xmmregs[t0reg].inuse )
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break;
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}
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if( t0reg < XMMREGS ) {
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if (t0reg < XMMREGS )
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{
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SSE_MOVHLPS_XMM_to_XMM(t0reg, i);
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SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[i].reg), i);
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SSE_MOVSS_XMM_to_M32(VU_VFx_ADDR(xmmregs[i].reg)+8, t0reg);
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}
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else {
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else
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{
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// no free reg
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SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[i].reg), i);
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SSE_SHUFPS_XMM_to_XMM(i, i, 0xc6);
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@ -660,7 +692,8 @@ void _deleteVFtoXMMreg(int reg, int vu, int flush)
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SSE_SHUFPS_XMM_to_XMM(i, i, 0xc6);
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}
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}
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else {
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else
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{
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// xy
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SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[i].reg), i);
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}
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@ -672,8 +705,7 @@ void _deleteVFtoXMMreg(int reg, int vu, int flush)
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xmmregs[i].mode |= MODE_READ;
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}
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if( flush == 2 )
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xmmregs[i].inuse = 0;
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if (flush == 2) xmmregs[i].inuse = 0;
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break;
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}
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@ -688,8 +720,7 @@ void _deleteACCtoXMMreg(int vu, int flush)
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VURegs *VU = vu ? &VU1 : &VU0;
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for (i=0; i<XMMREGS; i++) {
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if (xmmregs[i].inuse && xmmregs[i].type == XMMTYPE_ACC && xmmregs[i].VU == vu) {
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if (xmmregs[i].inuse && (xmmregs[i].type == XMMTYPE_ACC) && (xmmregs[i].VU == vu)) {
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switch(flush) {
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case 0:
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@ -806,28 +837,34 @@ void _deleteFPtoXMMreg(int reg, int flush)
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}
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}
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void _freeXMMreg(int xmmreg) {
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void _freeXMMreg(int xmmreg)
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{
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VURegs *VU = xmmregs[xmmreg].VU ? &VU1 : &VU0;
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assert( xmmreg < XMMREGS );
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if (!xmmregs[xmmreg].inuse) return;
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if (xmmregs[xmmreg].type == XMMTYPE_VFREG && (xmmregs[xmmreg].mode & MODE_WRITE) ) {
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if( xmmregs[xmmreg].mode & MODE_VUXYZ ) {
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if( xmmregs[xmmreg].mode & MODE_VUZ ) {
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if (xmmregs[xmmreg].mode & MODE_WRITE) {
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switch (xmmregs[xmmreg].type) {
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case XMMTYPE_VFREG:
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if( xmmregs[xmmreg].mode & MODE_VUXYZ )
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{
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if( xmmregs[xmmreg].mode & MODE_VUZ )
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{
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// don't destroy w
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int t0reg;
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for(t0reg = 0; t0reg < XMMREGS; ++t0reg ) {
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if( !xmmregs[t0reg].inuse ) break;
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}
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if( t0reg < XMMREGS ) {
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if( t0reg < XMMREGS )
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{
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SSE_MOVHLPS_XMM_to_XMM(t0reg, xmmreg);
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SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
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SSE_MOVSS_XMM_to_M32(VU_VFx_ADDR(xmmregs[xmmreg].reg)+8, t0reg);
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}
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else {
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else
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{
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// no free reg
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SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
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SSE_SHUFPS_XMM_to_XMM(xmmreg, xmmreg, 0xc6);
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@ -836,28 +873,37 @@ void _freeXMMreg(int xmmreg) {
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SSE_SHUFPS_XMM_to_XMM(xmmreg, xmmreg, 0xc6);
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}
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}
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else {
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else
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{
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SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
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}
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}
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else SSE_MOVAPS_XMM_to_M128(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
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else
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{
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SSE_MOVAPS_XMM_to_M128(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
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}
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else if (xmmregs[xmmreg].type == XMMTYPE_ACC && (xmmregs[xmmreg].mode & MODE_WRITE) ) {
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if( xmmregs[xmmreg].mode & MODE_VUXYZ ) {
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break;
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||||
if( xmmregs[xmmreg].mode & MODE_VUZ ) {
|
||||
case XMMTYPE_ACC:
|
||||
if( xmmregs[xmmreg].mode & MODE_VUXYZ )
|
||||
{
|
||||
if( xmmregs[xmmreg].mode & MODE_VUZ )
|
||||
{
|
||||
// don't destroy w
|
||||
int t0reg;
|
||||
|
||||
for(t0reg = 0; t0reg < XMMREGS; ++t0reg ) {
|
||||
if( !xmmregs[t0reg].inuse ) break;
|
||||
}
|
||||
|
||||
if( t0reg < XMMREGS ) {
|
||||
if( t0reg < XMMREGS )
|
||||
{
|
||||
SSE_MOVHLPS_XMM_to_XMM(t0reg, xmmreg);
|
||||
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, xmmreg);
|
||||
SSE_MOVSS_XMM_to_M32(VU_ACCx_ADDR+8, t0reg);
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
// no free reg
|
||||
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, xmmreg);
|
||||
SSE_SHUFPS_XMM_to_XMM(xmmreg, xmmreg, 0xc6);
|
||||
|
|
@ -866,24 +912,35 @@ void _freeXMMreg(int xmmreg) {
|
|||
SSE_SHUFPS_XMM_to_XMM(xmmreg, xmmreg, 0xc6);
|
||||
}
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, xmmreg);
|
||||
}
|
||||
}
|
||||
else SSE_MOVAPS_XMM_to_M128(VU_ACCx_ADDR, xmmreg);
|
||||
else
|
||||
{
|
||||
SSE_MOVAPS_XMM_to_M128(VU_ACCx_ADDR, xmmreg);
|
||||
}
|
||||
else if (xmmregs[xmmreg].type == XMMTYPE_GPRREG && (xmmregs[xmmreg].mode & MODE_WRITE) ) {
|
||||
break;
|
||||
|
||||
case XMMTYPE_GPRREG:
|
||||
assert( xmmregs[xmmreg].reg != 0 );
|
||||
//assert( g_xmmtypes[xmmreg] == XMMT_INT );
|
||||
SSEX_MOVDQA_XMM_to_M128((uptr)&cpuRegs.GPR.r[xmmregs[xmmreg].reg].UL[0], xmmreg);
|
||||
}
|
||||
else if (xmmregs[xmmreg].type == XMMTYPE_FPREG && (xmmregs[xmmreg].mode & MODE_WRITE)) {
|
||||
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[xmmregs[xmmreg].reg], xmmreg);
|
||||
}
|
||||
else if (xmmregs[xmmreg].type == XMMTYPE_FPACC && (xmmregs[xmmreg].mode & MODE_WRITE)) {
|
||||
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.ACC.f, xmmreg);
|
||||
}
|
||||
break;
|
||||
|
||||
case XMMTYPE_FPREG:
|
||||
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[xmmregs[xmmreg].reg], xmmreg);
|
||||
break;
|
||||
|
||||
case XMMTYPE_FPACC:
|
||||
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.ACC.f, xmmreg);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
xmmregs[xmmreg].mode &= ~(MODE_WRITE|MODE_VUXYZ);
|
||||
xmmregs[xmmreg].inuse = 0;
|
||||
}
|
||||
|
|
@ -1184,12 +1241,13 @@ void _recClearInst(EEINST* pinst)
|
|||
}
|
||||
|
||||
// returns nonzero value if reg has been written between [startpc, endpc-4]
|
||||
int _recIsRegWritten(EEINST* pinst, int size, u8 xmmtype, u8 reg)
|
||||
u32 _recIsRegWritten(EEINST* pinst, int size, u8 xmmtype, u8 reg)
|
||||
{
|
||||
int i, inst = 1;
|
||||
u32 i, inst = 1;
|
||||
|
||||
while(size-- > 0) {
|
||||
for(i = 0; i < ARRAYSIZE(pinst->writeType); ++i) {
|
||||
if( pinst->writeType[i] == xmmtype && pinst->writeReg[i] == reg )
|
||||
if ((pinst->writeType[i] == xmmtype) && (pinst->writeReg[i] == reg))
|
||||
return inst;
|
||||
}
|
||||
++inst;
|
||||
|
|
@ -1199,9 +1257,9 @@ int _recIsRegWritten(EEINST* pinst, int size, u8 xmmtype, u8 reg)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int _recIsRegUsed(EEINST* pinst, int size, u8 xmmtype, u8 reg)
|
||||
u32 _recIsRegUsed(EEINST* pinst, int size, u8 xmmtype, u8 reg)
|
||||
{
|
||||
int i, inst = 1;
|
||||
u32 i, inst = 1;
|
||||
while(size-- > 0) {
|
||||
for(i = 0; i < ARRAYSIZE(pinst->writeType); ++i) {
|
||||
if( pinst->writeType[i] == xmmtype && pinst->writeReg[i] == reg )
|
||||
|
|
@ -1220,8 +1278,8 @@ int _recIsRegUsed(EEINST* pinst, int size, u8 xmmtype, u8 reg)
|
|||
|
||||
void _recFillRegister(EEINST* pinst, int type, int reg, int write)
|
||||
{
|
||||
int i = 0;
|
||||
if( write ) {
|
||||
u32 i = 0;
|
||||
if (write ) {
|
||||
for(i = 0; i < ARRAYSIZE(pinst->writeType); ++i) {
|
||||
if( pinst->writeType[i] == XMMTYPE_TEMP ) {
|
||||
pinst->writeType[i] = type;
|
||||
|
|
|
|||
|
|
@ -323,9 +323,9 @@ extern EEINST* g_pCurInstInfo; // info for the cur instruction
|
|||
void _recClearInst(EEINST* pinst);
|
||||
|
||||
// returns the number of insts + 1 until written (0 if not written)
|
||||
int _recIsRegWritten(EEINST* pinst, int size, u8 xmmtype, u8 reg);
|
||||
u32 _recIsRegWritten(EEINST* pinst, int size, u8 xmmtype, u8 reg);
|
||||
// returns the number of insts + 1 until used (0 if not used)
|
||||
int _recIsRegUsed(EEINST* pinst, int size, u8 xmmtype, u8 reg);
|
||||
u32 _recIsRegUsed(EEINST* pinst, int size, u8 xmmtype, u8 reg);
|
||||
void _recFillRegister(EEINST* pinst, int type, int reg, int write);
|
||||
|
||||
#define EEINST_ISLIVE64(reg) (g_pCurInstInfo->regs[reg] & (EEINST_LIVE0|EEINST_LIVE1))
|
||||
|
|
|
|||
Loading…
Reference in New Issue