mirror of https://github.com/PCSX2/pcsx2.git
microVU: Added some const qualifiers to the instruction/opcode function LUTs
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3548 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -223,6 +223,7 @@ extern VIFregisters *vifRegs;
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#define vifXRegs (idx ? (vif1Regs) : (vif0Regs))
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#define vifXCode (idx ? (vif1Code) : (vif0Code))
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#define _f __forceinline
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#define _ri __releaseinline
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extern void dmaVIF0();
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extern void dmaVIF1();
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@ -60,8 +60,8 @@ struct GIFTAG
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{
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u32 NLOOP : 15;
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u32 EOP : 1;
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u32 dummy0 : 16;
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u32 dummy1 : 14;
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u32 _dummy0 : 16;
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u32 _dummy1 : 14;
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u32 PRE : 1;
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u32 PRIM : 11;
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u32 FLG : 2;
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@ -17,6 +17,11 @@
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using namespace x86Emitter;
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typedef xRegisterSSE xmm;
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typedef xRegister32 x32;
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struct microVU;
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//------------------------------------------------------------------
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// Global Variables
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//------------------------------------------------------------------
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@ -34,9 +39,6 @@ struct mVU_Globals {
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extern const __aligned(32) mVU_Globals mVUglob;
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typedef xRegisterSSE xmm;
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typedef xRegister32 x32;
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//------------------------------------------------------------------
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// Helper Macros
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//------------------------------------------------------------------
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@ -120,6 +122,9 @@ typedef xRegister32 x32;
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#define mF int recPass
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#define mX mVU, recPass
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typedef void __fastcall Fntype_mVUrecInst( microVU* mVU, int recPass );
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typedef Fntype_mVUrecInst* Fnptr_mVUrecInst;
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// Recursive Inline
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#ifndef __LINUX__
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#define __recInline __releaseinline
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@ -129,7 +134,7 @@ typedef xRegister32 x32;
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// Function/Template Stuff
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#define mVUx (vuIndex ? µVU1 : µVU0)
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#define mVUop(opName) static void opName (mP)
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#define mVUop(opName) static void __fastcall opName (mP)
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#define _mVUt template<int vuIndex>
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#define _r static __recInline
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@ -33,7 +33,7 @@ mVUop(mVUunknown);
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//------------------------------------------------------------------
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// Opcode Tables
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//------------------------------------------------------------------
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void (*mVULOWER_OPCODE [128])(mP) = {
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static const Fnptr_mVUrecInst mVULOWER_OPCODE[128] = {
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mVU_LQ , mVU_SQ , mVUunknown , mVUunknown,
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mVU_ILW , mVU_ISW , mVUunknown , mVUunknown,
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mVU_IADDIU , mVU_ISUBIU , mVUunknown , mVUunknown,
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@ -68,7 +68,7 @@ void (*mVULOWER_OPCODE [128])(mP) = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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};
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void (*mVULowerOP_T3_00_OPCODE [32])(mP) = {
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static const Fnptr_mVUrecInst mVULowerOP_T3_00_OPCODE[32] = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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@ -79,7 +79,7 @@ void (*mVULowerOP_T3_00_OPCODE [32])(mP) = {
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mVU_ESADD , mVU_EATANxy , mVU_ESQRT , mVU_ESIN,
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};
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void (*mVULowerOP_T3_01_OPCODE [32])(mP) = {
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static const Fnptr_mVUrecInst mVULowerOP_T3_01_OPCODE[32] = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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@ -90,7 +90,7 @@ void (*mVULowerOP_T3_01_OPCODE [32])(mP) = {
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mVU_ERSADD , mVU_EATANxz , mVU_ERSQRT , mVU_EATAN,
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};
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void (*mVULowerOP_T3_10_OPCODE [32])(mP) = {
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static const Fnptr_mVUrecInst mVULowerOP_T3_10_OPCODE[32] = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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@ -101,7 +101,7 @@ void (*mVULowerOP_T3_10_OPCODE [32])(mP) = {
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mVU_ELENG , mVU_ESUM , mVU_ERCPR , mVU_EEXP,
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};
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void (*mVULowerOP_T3_11_OPCODE [32])(mP) = {
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const Fnptr_mVUrecInst mVULowerOP_T3_11_OPCODE [32] = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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@ -112,7 +112,7 @@ void (*mVULowerOP_T3_11_OPCODE [32])(mP) = {
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mVU_ERLENG , mVUunknown , mVU_WAITP , mVUunknown,
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};
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void (*mVULowerOP_OPCODE [64])(mP) = {
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static const Fnptr_mVUrecInst mVULowerOP_OPCODE[64] = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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@ -131,7 +131,7 @@ void (*mVULowerOP_OPCODE [64])(mP) = {
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mVULowerOP_T3_00, mVULowerOP_T3_01, mVULowerOP_T3_10, mVULowerOP_T3_11,
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};
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void (*mVU_UPPER_OPCODE [64])(mP) = {
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static const Fnptr_mVUrecInst mVU_UPPER_OPCODE[64] = {
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mVU_ADDx , mVU_ADDy , mVU_ADDz , mVU_ADDw,
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mVU_SUBx , mVU_SUBy , mVU_SUBz , mVU_SUBw,
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mVU_MADDx , mVU_MADDy , mVU_MADDz , mVU_MADDw,
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@ -150,7 +150,7 @@ void (*mVU_UPPER_OPCODE [64])(mP) = {
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mVU_UPPER_FD_00, mVU_UPPER_FD_01, mVU_UPPER_FD_10, mVU_UPPER_FD_11,
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};
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void (*mVU_UPPER_FD_00_TABLE [32])(mP) = {
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static const Fnptr_mVUrecInst mVU_UPPER_FD_00_TABLE [32] = {
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mVU_ADDAx , mVU_SUBAx , mVU_MADDAx , mVU_MSUBAx,
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mVU_ITOF0 , mVU_FTOI0 , mVU_MULAx , mVU_MULAq,
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mVU_ADDAq , mVU_SUBAq , mVU_ADDA , mVU_SUBA,
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@ -161,7 +161,7 @@ void (*mVU_UPPER_FD_00_TABLE [32])(mP) = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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};
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void (* mVU_UPPER_FD_01_TABLE [32])(mP) = {
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static const Fnptr_mVUrecInst mVU_UPPER_FD_01_TABLE [32] = {
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mVU_ADDAy , mVU_SUBAy , mVU_MADDAy , mVU_MSUBAy,
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mVU_ITOF4 , mVU_FTOI4 , mVU_MULAy , mVU_ABS,
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mVU_MADDAq , mVU_MSUBAq , mVU_MADDA , mVU_MSUBA,
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@ -172,7 +172,7 @@ void (* mVU_UPPER_FD_01_TABLE [32])(mP) = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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};
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void (* mVU_UPPER_FD_10_TABLE [32])(mP) = {
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static const Fnptr_mVUrecInst mVU_UPPER_FD_10_TABLE [32] = {
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mVU_ADDAz , mVU_SUBAz , mVU_MADDAz , mVU_MSUBAz,
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mVU_ITOF12 , mVU_FTOI12 , mVU_MULAz , mVU_MULAi,
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mVU_ADDAi , mVU_SUBAi , mVU_MULA , mVU_OPMULA,
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@ -183,7 +183,7 @@ void (* mVU_UPPER_FD_10_TABLE [32])(mP) = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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};
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void (* mVU_UPPER_FD_11_TABLE [32])(mP) = {
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static const Fnptr_mVUrecInst mVU_UPPER_FD_11_TABLE [32] = {
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mVU_ADDAw , mVU_SUBAw , mVU_MADDAw , mVU_MSUBAw,
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mVU_ITOF15 , mVU_FTOI15 , mVU_MULAw , mVU_CLIP,
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mVU_MADDAi , mVU_MSUBAi , mVUunknown , mVU_NOP,
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