mirror of https://github.com/PCSX2/pcsx2.git
psxmode: further spu2x work
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3aabc1adbf
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08b6edae80
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@ -214,10 +214,7 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
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else
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else
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DMA7LogWrite(pMem,size<<1);
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DMA7LogWrite(pMem,size<<1);
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if (psxmode)
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TSA &= 0xfffff;
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TSA &= 0x7ffff;
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else
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TSA &= 0xfffff;
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u32 buff1end = TSA + size;
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u32 buff1end = TSA + size;
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u32 buff2end=0;
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u32 buff2end=0;
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@ -238,11 +235,14 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
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cacheLine++;
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cacheLine++;
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} while ( cacheLine != &cacheEnd );
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} while ( cacheLine != &cacheEnd );
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//ConLog( "* SPU2-X: Cache Clear Range! TSA=0x%x, TDA=0x%x (low8=0x%x, high8=0x%x, len=0x%x)\n",
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// TSA, buff1end, flagTSA, flagTDA, clearLen );
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// First Branch needs cleared:
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// First Branch needs cleared:
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// It starts at TSA and goes to buff1end.
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// It starts at TSA and goes to buff1end.
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const u32 buff1size = (buff1end-TSA);
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const u32 buff1size = (buff1end-TSA);
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ConLog("* SPU2-X: DMA exec! TSA = %x buff1size*2 = %x\n", TSA, buff1size*2);
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memcpy( GetMemPtr( TSA ), pMem, buff1size*2 );
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memcpy( GetMemPtr( TSA ), pMem, buff1size*2 );
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u32 TDA;
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u32 TDA;
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@ -261,8 +261,7 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
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// 0x2800? Hard to know for sure (almost no games depend on this)
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// 0x2800? Hard to know for sure (almost no games depend on this)
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memcpy( GetMemPtr( 0 ), &pMem[buff1size], buff2end*2 );
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memcpy( GetMemPtr( 0 ), &pMem[buff1size], buff2end*2 );
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if (psxmode) TDA = (buff2end + 1) & 0x7ffff;
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TDA = (buff2end+1) & 0xfffff;
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else TDA = (buff2end+1) & 0xfffff;
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Important: Test both core IRQ settings for either DMA!
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// Important: Test both core IRQ settings for either DMA!
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@ -298,8 +297,7 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
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// Buffer doesn't wrap/overflow!
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// Buffer doesn't wrap/overflow!
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// Just set the TDA and check for an IRQ...
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// Just set the TDA and check for an IRQ...
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if (psxmode) TDA = (buff1end + 1) & 0x7ffff;
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TDA = (buff1end + 1) & 0xfffff;
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else TDA = (buff1end + 1) & 0xfffff;
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Flag interrupt? If IRQA occurs between start and dest, flag it.
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// Important: Test both core IRQ settings for either DMA!
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// Important: Test both core IRQ settings for either DMA!
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@ -404,7 +402,6 @@ void V_Core::DoDMAwrite(u16* pMem, u32 size)
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if(size<2) {
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if(size<2) {
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//if(dma7callback) dma7callback();
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//if(dma7callback) dma7callback();
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ConLog("* SPU2-X: Warning DMA Transfer of 0 bytes? size is %x\n", size);
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Regs.STATX &= ~0x80;
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Regs.STATX &= ~0x80;
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//Regs.ATTR |= 0x30;
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//Regs.ATTR |= 0x30;
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DMAICounter=1;
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DMAICounter=1;
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@ -425,12 +422,11 @@ void V_Core::DoDMAwrite(u16* pMem, u32 size)
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}
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}
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}
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}
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if (psxmode) TSA &= 0x7ffff;
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TSA &= 0xfffff;
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else TSA &= 0xfffff;
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bool adma_enable = ((AutoDMACtrl&(Index+1))==(Index+1));
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bool adma_enable = ((AutoDMACtrl&(Index+1))==(Index+1));
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if(adma_enable && !psxmode) // no adma in psx mode
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if(adma_enable)
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{
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{
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TSA&=0x1fff;
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TSA&=0x1fff;
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StartADMAWrite(pMem,size);
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StartADMAWrite(pMem,size);
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@ -556,7 +556,7 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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thisvol.Mode = 0;
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thisvol.Mode = 0;
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thisvol.Increment = 0;
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thisvol.Increment = 0;
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}
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}
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//ConLog("voice %x VOLL write: %x\n", voice, value);
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ConLog("voice %x VOLL write: %x\n", voice, value);
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break;
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break;
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}
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}
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case 0x2: //VOLR (Volume R)
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case 0x2: //VOLR (Volume R)
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@ -581,7 +581,7 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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thisvol.Mode = 0;
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thisvol.Mode = 0;
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thisvol.Increment = 0;
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thisvol.Increment = 0;
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}
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}
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//ConLog("voice %x VOLR write: %x\n", voice, value);
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ConLog("voice %x VOLR write: %x\n", voice, value);
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break;
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break;
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}
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}
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case 0x4:
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case 0x4:
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@ -607,7 +607,7 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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case 0xc: // Voice 0..23 ADSR Current Volume
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case 0xc: // Voice 0..23 ADSR Current Volume
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// not commonly set by games
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// not commonly set by games
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Voices[voice].ADSR.Value = (value << 16) | value;
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Voices[voice].ADSR.Value = (value << 16) | value;
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//ConLog("voice %x ADSR.Value write: %x\n", voice, Voices[voice].ADSR.Value);
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ConLog("voice %x ADSR.Value write: %x\n", voice, Voices[voice].ADSR.Value);
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break;
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break;
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case 0xe:
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case 0xe:
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Voices[voice].LoopStartA = value * 8;
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Voices[voice].LoopStartA = value * 8;
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@ -723,13 +723,13 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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case 0x1da4:
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case 0x1da4:
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IRQA = value * 8;
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IRQA = value * 8;
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psxIRQA = value;
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psxIRQA = value;
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ConLog("SPU2-X Setting IRQA to %x value was %x \n", IRQA, value);
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ConLog("SPU2-X Setting IRQA to %x \n", IRQA);
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break;
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break;
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case 0x1da6:
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case 0x1da6:
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TSA = value * 8;
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TSA = value * 8;
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psxTSA = value;
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psxTSA = value;
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ConLog("SPU2-X Setting TSA to %x value was %x \n", TSA, value);
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ConLog("SPU2-X Setting TSA to %x \n", TSA);
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break;
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break;
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case 0x1da8: // Spu Write to Memory
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case 0x1da8: // Spu Write to Memory
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@ -740,6 +740,7 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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_irqcallback();
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_irqcallback();
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}
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}
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DmaWritePSX(value);
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DmaWritePSX(value);
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//DmaWrite(value);
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show = false;
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show = false;
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break;
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break;
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@ -1337,19 +1338,6 @@ static void __fastcall RegWrite_Core( u16 value )
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Cores[1].ReverbX = 0;
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Cores[1].ReverbX = 0;
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Cores[1].RevBuffers.NeedsUpdated = true;
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Cores[1].RevBuffers.NeedsUpdated = true;
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Cores[1].Mute = 1; // silence core1 in psxmode
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Cores[1].Mute = 1; // silence core1 in psxmode
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//for (uint v = 0; v < 24; ++v)
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//{
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// Cores[0].Voices[v].Volume = V_VolumeSlideLR(0, 0); // V_VolumeSlideLR::Max;
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// Cores[0].Voices[v].SCurrent = 28;
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// Cores[0].Voices[v].ADSR.Value = 0;
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// Cores[0].Voices[v].ADSR.Phase = 0;
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// Cores[0].Voices[v].Pitch = 0x1000;
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// Cores[0].Voices[v].NextA = 0x1001;
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// Cores[0].Voices[v].StartA = 0x1000;
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// Cores[0].Voices[v].LoopStartA = 0x1000;
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// Cores[0].Voices[v].Modulated = 0;
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//}
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for (uint v = 0; v < 24; ++v)
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for (uint v = 0; v < 24; ++v)
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{
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{
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Cores[1].Voices[v].Volume = V_VolumeSlideLR(0, 0); // V_VolumeSlideLR::Max;
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Cores[1].Voices[v].Volume = V_VolumeSlideLR(0, 0); // V_VolumeSlideLR::Max;
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