mirror of https://github.com/PCSX2/pcsx2.git
psxmode: further spu2x work
This commit is contained in:
parent
3aabc1adbf
commit
08b6edae80
|
@ -214,10 +214,7 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
|
|||
else
|
||||
DMA7LogWrite(pMem,size<<1);
|
||||
|
||||
if (psxmode)
|
||||
TSA &= 0x7ffff;
|
||||
else
|
||||
TSA &= 0xfffff;
|
||||
TSA &= 0xfffff;
|
||||
|
||||
u32 buff1end = TSA + size;
|
||||
u32 buff2end=0;
|
||||
|
@ -238,11 +235,14 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
|
|||
cacheLine++;
|
||||
} while ( cacheLine != &cacheEnd );
|
||||
|
||||
//ConLog( "* SPU2-X: Cache Clear Range! TSA=0x%x, TDA=0x%x (low8=0x%x, high8=0x%x, len=0x%x)\n",
|
||||
// TSA, buff1end, flagTSA, flagTDA, clearLen );
|
||||
|
||||
|
||||
// First Branch needs cleared:
|
||||
// It starts at TSA and goes to buff1end.
|
||||
|
||||
const u32 buff1size = (buff1end-TSA);
|
||||
ConLog("* SPU2-X: DMA exec! TSA = %x buff1size*2 = %x\n", TSA, buff1size*2);
|
||||
memcpy( GetMemPtr( TSA ), pMem, buff1size*2 );
|
||||
|
||||
u32 TDA;
|
||||
|
@ -261,8 +261,7 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
|
|||
// 0x2800? Hard to know for sure (almost no games depend on this)
|
||||
|
||||
memcpy( GetMemPtr( 0 ), &pMem[buff1size], buff2end*2 );
|
||||
if (psxmode) TDA = (buff2end + 1) & 0x7ffff;
|
||||
else TDA = (buff2end+1) & 0xfffff;
|
||||
TDA = (buff2end+1) & 0xfffff;
|
||||
|
||||
// Flag interrupt? If IRQA occurs between start and dest, flag it.
|
||||
// Important: Test both core IRQ settings for either DMA!
|
||||
|
@ -298,8 +297,7 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
|
|||
// Buffer doesn't wrap/overflow!
|
||||
// Just set the TDA and check for an IRQ...
|
||||
|
||||
if (psxmode) TDA = (buff1end + 1) & 0x7ffff;
|
||||
else TDA = (buff1end + 1) & 0xfffff;
|
||||
TDA = (buff1end + 1) & 0xfffff;
|
||||
|
||||
// Flag interrupt? If IRQA occurs between start and dest, flag it.
|
||||
// Important: Test both core IRQ settings for either DMA!
|
||||
|
@ -404,7 +402,6 @@ void V_Core::DoDMAwrite(u16* pMem, u32 size)
|
|||
|
||||
if(size<2) {
|
||||
//if(dma7callback) dma7callback();
|
||||
ConLog("* SPU2-X: Warning DMA Transfer of 0 bytes? size is %x\n", size);
|
||||
Regs.STATX &= ~0x80;
|
||||
//Regs.ATTR |= 0x30;
|
||||
DMAICounter=1;
|
||||
|
@ -425,12 +422,11 @@ void V_Core::DoDMAwrite(u16* pMem, u32 size)
|
|||
}
|
||||
}
|
||||
|
||||
if (psxmode) TSA &= 0x7ffff;
|
||||
else TSA &= 0xfffff;
|
||||
TSA &= 0xfffff;
|
||||
|
||||
bool adma_enable = ((AutoDMACtrl&(Index+1))==(Index+1));
|
||||
|
||||
if(adma_enable && !psxmode) // no adma in psx mode
|
||||
if(adma_enable)
|
||||
{
|
||||
TSA&=0x1fff;
|
||||
StartADMAWrite(pMem,size);
|
||||
|
|
|
@ -556,7 +556,7 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
|
|||
thisvol.Mode = 0;
|
||||
thisvol.Increment = 0;
|
||||
}
|
||||
//ConLog("voice %x VOLL write: %x\n", voice, value);
|
||||
ConLog("voice %x VOLL write: %x\n", voice, value);
|
||||
break;
|
||||
}
|
||||
case 0x2: //VOLR (Volume R)
|
||||
|
@ -581,7 +581,7 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
|
|||
thisvol.Mode = 0;
|
||||
thisvol.Increment = 0;
|
||||
}
|
||||
//ConLog("voice %x VOLR write: %x\n", voice, value);
|
||||
ConLog("voice %x VOLR write: %x\n", voice, value);
|
||||
break;
|
||||
}
|
||||
case 0x4:
|
||||
|
@ -607,7 +607,7 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
|
|||
case 0xc: // Voice 0..23 ADSR Current Volume
|
||||
// not commonly set by games
|
||||
Voices[voice].ADSR.Value = (value << 16) | value;
|
||||
//ConLog("voice %x ADSR.Value write: %x\n", voice, Voices[voice].ADSR.Value);
|
||||
ConLog("voice %x ADSR.Value write: %x\n", voice, Voices[voice].ADSR.Value);
|
||||
break;
|
||||
case 0xe:
|
||||
Voices[voice].LoopStartA = value * 8;
|
||||
|
@ -723,13 +723,13 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
|
|||
case 0x1da4:
|
||||
IRQA = value * 8;
|
||||
psxIRQA = value;
|
||||
ConLog("SPU2-X Setting IRQA to %x value was %x \n", IRQA, value);
|
||||
ConLog("SPU2-X Setting IRQA to %x \n", IRQA);
|
||||
break;
|
||||
|
||||
case 0x1da6:
|
||||
TSA = value * 8;
|
||||
psxTSA = value;
|
||||
ConLog("SPU2-X Setting TSA to %x value was %x \n", TSA, value);
|
||||
ConLog("SPU2-X Setting TSA to %x \n", TSA);
|
||||
break;
|
||||
|
||||
case 0x1da8: // Spu Write to Memory
|
||||
|
@ -740,6 +740,7 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
|
|||
_irqcallback();
|
||||
}
|
||||
DmaWritePSX(value);
|
||||
//DmaWrite(value);
|
||||
show = false;
|
||||
break;
|
||||
|
||||
|
@ -1337,19 +1338,6 @@ static void __fastcall RegWrite_Core( u16 value )
|
|||
Cores[1].ReverbX = 0;
|
||||
Cores[1].RevBuffers.NeedsUpdated = true;
|
||||
Cores[1].Mute = 1; // silence core1 in psxmode
|
||||
//for (uint v = 0; v < 24; ++v)
|
||||
//{
|
||||
// Cores[0].Voices[v].Volume = V_VolumeSlideLR(0, 0); // V_VolumeSlideLR::Max;
|
||||
// Cores[0].Voices[v].SCurrent = 28;
|
||||
|
||||
// Cores[0].Voices[v].ADSR.Value = 0;
|
||||
// Cores[0].Voices[v].ADSR.Phase = 0;
|
||||
// Cores[0].Voices[v].Pitch = 0x1000;
|
||||
// Cores[0].Voices[v].NextA = 0x1001;
|
||||
// Cores[0].Voices[v].StartA = 0x1000;
|
||||
// Cores[0].Voices[v].LoopStartA = 0x1000;
|
||||
// Cores[0].Voices[v].Modulated = 0;
|
||||
//}
|
||||
for (uint v = 0; v < 24; ++v)
|
||||
{
|
||||
Cores[1].Voices[v].Volume = V_VolumeSlideLR(0, 0); // V_VolumeSlideLR::Max;
|
||||
|
|
Loading…
Reference in New Issue