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some EE rec and interpreter opcode fixes. theres still some possible problems with the rec opcodes, not sure how i'm going to fix it yet. anyways, should be alot better than it was before. 

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@173 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes 2008-10-06 21:39:20 +00:00 committed by Gregory Hainaut
parent c734750dde
commit 06d3b9731b
4 changed files with 28 additions and 32 deletions
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6
pcsx2/Interpreter.c
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@ -147,9 +147,9 @@ void ADDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_
void ADDIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SL[0] + _Imm_; }// Rt = Rs + Im signed !!!
void DADDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] + _Imm_; }// Rt = Rs + Im
void DADDIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] + _Imm_; }// Rt = Rs + Im
void ANDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] & (s64)_ImmU_; } // Rt = Rs And Im
void ORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] | (s64)_ImmU_; } // Rt = Rs Or Im
void XORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] ^ (s64)_ImmU_; } // Rt = Rs Xor Im
void ANDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] & (u64)_ImmU_; } // Rt = Rs And Im (zero-extended)
void ORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] | (s64)_ImmU_; } // Rt = Rs Or Im (sign-extended)
void XORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] ^ (u64)_ImmU_; } // Rt = Rs Xor Im (zero-extended)
void SLTI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] < (s64)(_Imm_); } // Rt = Rs < Im (signed)
void SLTIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] < (u64)(_Imm_); } // Rt = Rs < Im (unsigned)

1
pcsx2/R5900.h
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@ -211,6 +211,7 @@ extern PCSX2_ALIGNED16_DECL(tlbs tlb[48]);
#define _Imm_ ((s16)cpuRegs.code) // sign-extended immediate
#define _ImmU_ (cpuRegs.code&0xffff) // zero-extended immediate
#define _ImmSB_ (cpuRegs.code&0x8000) // gets the sign-bit of the immediate value
//#define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction

4
pcsx2/windows/pcsx2.rc
View File

@ -1046,7 +1046,7 @@ BEGIN
"Button",BS_AUTOCHECKBOX | WS_TABSTOP,15,162,418,10
CONTROL "Disable VU Overflow Checks - *Checked = Disables overflow checks. ( Speedup! ) *Greyed = Extra overflow checks. ( Helps SPS, Slow! )",IDC_VU_OVERFLOWHACK,
"Button",BS_AUTO3STATE | WS_TABSTOP,15,49,475,10
CTEXT "These hacks will effect the speed of PCSX2 but possibly compromise on compatibility",IDC_HACKDESC,7,7,497,8
CTEXT "These hacks will affect the speed of PCSX2 but possibly compromise compatibility.",IDC_HACKDESC,7,7,497,8
CONTROL "Tighter SPU2 Sync ( FFXII vids) - Slower, not very useful anymore.",IDC_SOUNDHACK,
"Button",BS_AUTOCHECKBOX | WS_TABSTOP,15,245,421,10
CONTROL "IOP Sync Hack (x2) - Doubles the cycle rate of the IOP. ( Speedup but breaks some games. )",IDC_SYNCHACK2,
@ -1057,7 +1057,7 @@ BEGIN
"Button",BS_AUTO3STATE | WS_TABSTOP,15,63,483,10
CONTROL "EE/IOP Fast Branches - Quick branching ( Very small speedup; Not Recommended! )",IDC_FASTBRANCHES,
"Button",BS_AUTOCHECKBOX | WS_TABSTOP,15,231,423,10
CTEXT "If you have problems, disable all these and try again",IDC_STATIC,7,22,497,8
CTEXT "If you have problems, disable all these and try again!",IDC_STATIC,7,22,497,8
GROUPBOX "Overflow and Underflow",IDC_STATIC,7,36,497,58
CONTROL "Disable Underflow Checks - *Checked = Disables underflow checks. ( Speedup! )",IDC_DENORMALS,
"Button",BS_AUTOCHECKBOX | WS_TABSTOP,15,77,319,10

49
pcsx2/x86/ix86-32/iR5900AritImm.c
View File

@ -340,7 +340,7 @@ EERECOMPILE_CODEX(eeRecompileCode1, SLTI);
//// ANDI
void recANDI_const()
{
g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] & (s64)_ImmU_;
g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] & (u64)_ImmU_; // should be zero-extended
}
extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op);
@ -356,49 +356,41 @@ void recLogicalOpI(int info, int op)
SetMMXstate();
if( _ImmU_ != 0 ) {
u32* ptempmem = recAllocStackMem(8, 8);
ptempmem[0] = _ImmU_;
ptempmem[1] = 0;
u64* ptempmem = recAllocStackMem(8, 8);
*ptempmem = (op == 1) ? (s64)_ImmU_ : (u64)_ImmU_; // for ORI, IMM is sign-extended, for the others its zero-extended
if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
LogicalOpMtoR(EEREC_T, (u32)ptempmem, op);
}
else {
if( op == 0 ) PXORRtoR(EEREC_T, EEREC_T);
else {
if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
}
else if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
}
return;
}
if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) && ((_Rt_ != _Rs_) || (_ImmU_==0)) ) {
int rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE);
u32* ptempmem;
SetMMXstate();
ptempmem = recAllocStackMem(8, 8);
ptempmem[0] = _ImmU_;
ptempmem[1] = 0;
if( op == 0 ) {
if ( _ImmU_ != 0 ) {
if( _ImmU_ == 0xffff ) {
// take a shortcut
MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] - 2);
PSRLDItoR(rtreg, 16);
}
else {
MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
PANDMtoR(rtreg, (u32)ptempmem);
}
u64* ptempmem = recAllocStackMem(8, 8);
*ptempmem = (u64)_ImmU_; // for ANDI, IMM is zero-extended
MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
PANDMtoR(rtreg, (u32)ptempmem);
}
else PXORRtoR(rtreg, rtreg);
}
else {
MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
if ( _ImmU_ != 0 ) LogicalOpMtoR(rtreg, (u32)ptempmem, op);
if ( _ImmU_ != 0 ) {
u64* ptempmem = recAllocStackMem(8, 8);
*ptempmem = (op == 1) ? (s64)_ImmU_ : (u64)_ImmU_; // for ORI, IMM is sign-extended, for the others its zero-extended
LogicalOpMtoR(rtreg, (u32)ptempmem, op);
}
}
}
else {
@ -406,14 +398,17 @@ void recLogicalOpI(int info, int op)
{
if( _Rt_ == _Rs_ ) {
LogicalOp32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _ImmU_, op);
//LogicalOp32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], (_ImmSB_ && (op == 1)) ? 0xffffffff : 0, op);
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( op != 0 && EEINST_ISLIVE1(_Rt_) )
if( op != 0 && EEINST_ISLIVE1(_Rt_) ) {
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
LogicalOp32ItoR( EAX, _ImmU_, op);
if( op != 0 && EEINST_ISLIVE1(_Rt_) )
LogicalOp32ItoR( EAX, _ImmU_, op);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
}
else LogicalOp32ItoR( EAX, _ImmU_, op);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
}
@ -468,7 +463,7 @@ EERECOMPILE_CODEX(eeRecompileCode1, ORI);
////////////////////////////////////////////////////
void recXORI_const()
{
g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] ^ (s64)_ImmU_;
g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] ^ (u64)_ImmU_; // should be zero-extended
}
void recXORI_(int info)