mirror of https://github.com/PCSX2/pcsx2.git
microVU: 70% implemented Branch in Branch Delay Slots. Hopefully I'll finish tomorrow.
Compare Star Ocean 3 intro with mVU vs sVU, and you can see mVU now correctly renders the title menu/new game startup screen =) git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1652 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
614cc7e55d
commit
0587cdc210
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@ -159,6 +159,7 @@ struct microVU {
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u32 VIbackup; // Holds a backup of a VI reg if modified before a branch
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u32 VIxgkick; // Holds a backup of a VI reg used for xgkick-delays
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u32 branch; // Holds branch compare result (IBxx) OR Holds address to Jump to (JALR/JR)
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u32 evilBranch; // For Branches in Branch Delay Slots, holds Address to Jump to
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u32 p; // Holds current P instance index
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u32 q; // Holds current Q instance index
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u32 totalCycles; // Total Cycles that mVU is expected to run for
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@ -389,30 +389,31 @@ microVUt(void) analyzeBranchVI(mV, int xReg, bool &infoVar) {
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}
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// Branch in Branch Delay-Slots
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microVUt(void) mVUbranchCheck(mV) {
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if (!mVUcount) return;
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microVUt(int) mVUbranchCheck(mV) {
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if (!mVUcount) return 0;
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incPC(-2);
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if (mVUlow.branch) {
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incPC(2);
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Console::Error("microVU%d Warning: Branch in Branch delay slot! [%04x]", params mVU->index, xPC);
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mVUlow.isNOP = 1;
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mVUlow.evilBranch = 1;
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mVUregs.blockType = 2;
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DevCon::Status("microVU%d Warning: Branch in Branch delay slot! [%04x]", params mVU->index, xPC);
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return 1;
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}
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else incPC(2);
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incPC(2);
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return 0;
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}
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microVUt(void) mVUanalyzeCondBranch1(mV, int Is) {
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mVUbranchCheck(mVU);
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analyzeVIreg1(Is, mVUlow.VI_read[0]);
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if (!mVUstall) {
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if (!mVUstall && !mVUbranchCheck(mVU)) {
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analyzeBranchVI(mVU, Is, mVUlow.memReadIs);
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}
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}
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microVUt(void) mVUanalyzeCondBranch2(mV, int Is, int It) {
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mVUbranchCheck(mVU);
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analyzeVIreg1(Is, mVUlow.VI_read[0]);
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analyzeVIreg1(It, mVUlow.VI_read[1]);
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if (!mVUstall) {
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if (!mVUstall && !mVUbranchCheck(mVU)) {
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analyzeBranchVI(mVU, Is, mVUlow.memReadIs);
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analyzeBranchVI(mVU, It, mVUlow.memReadIt);
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}
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@ -96,9 +96,24 @@ void normBranchCompile(microVU* mVU, u32 branchPC) {
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else { mVUcompile(mVU, branchPC, (uptr)&mVUregs); }
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}
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void normBranch(mV, microFlagCycles& mFC) {
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void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump) {
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using namespace x86Emitter;
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memcpy_fast(&mVUpBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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mVUsetupBranch(mVU, mFC);
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mVUbackupRegs(mVU);
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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if (isEvilJump) MOV32MtoR(gprT2, (uptr)&mVU->evilBranch);
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else MOV32MtoR(gprT2, (uptr)&mVU->branch);
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MOV32ItoR(gprR, (u32)&mVUpBlock->pStateEnd);
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if (!mVU->index) xCALL(mVUcompileJIT<0>); //(u32 startPC, uptr pState)
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else xCALL(mVUcompileJIT<1>);
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mVUrestoreRegs(mVU);
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JMPR(gprT1); // Jump to rec-code address
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}
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void normBranch(mV, microFlagCycles& mFC) {
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// E-bit Branch
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if (mVUup.eBit) { iPC = branchAddr/4; mVUendProgram(mVU, &mFC, 1); return; }
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@ -112,6 +127,7 @@ void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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using namespace x86Emitter;
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mVUsetupBranch(mVU, mFC);
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xCMP(ptr16[&mVU->branch], 0);
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incPC(3);
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if (mVUup.eBit) { // Conditional Branch With E-Bit Set
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mVUendProgram(mVU, &mFC, 2);
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xForwardJump8 eJMP((JccComparisonType)JMPcc);
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@ -155,8 +171,6 @@ void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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void normJump(mV, microFlagCycles& mFC) {
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using namespace x86Emitter;
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mVUprint("mVUcompile JR/JALR");
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incPC(-3); // Go back to jump opcode
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if (mVUlow.constJump.isValid) { // Jump Address is Constant
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if (mVUup.eBit) { // E-bit Jump
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@ -175,18 +189,6 @@ void normJump(mV, microFlagCycles& mFC) {
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MOV32MtoR(gprT1, (uptr)&mVU->branch);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_TPC].UL, gprT1);
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xJMP(mVU->exitFunct);
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return;
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}
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memcpy_fast(&mVUpBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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mVUsetupBranch(mVU, mFC);
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mVUbackupRegs(mVU);
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MOV32MtoR(gprT2, (uptr)&mVU->branch); // Get startPC (ECX 1st argument for __fastcall)
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MOV32ItoR(gprR, (u32)&mVUpBlock->pStateEnd); // Get pState (EDX 2nd argument for __fastcall)
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if (!mVU->index) xCALL(mVUcompileJIT<0>); //(u32 startPC, uptr pState)
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else xCALL(mVUcompileJIT<1>);
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mVUrestoreRegs(mVU);
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JMPR(gprT1); // Jump to rec-code address
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else normJumpCompile(mVU, mFC, 0);
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}
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@ -174,14 +174,15 @@ microVUt(void) branchWarning(mV) {
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}
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microVUt(void) eBitPass1(mV, int& branch) {
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if (!mVUregs.blockType) {
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if (mVUregs.blockType != 1) {
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branch = 1;
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mVUup.eBit = 1;
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}
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}
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microVUt(void) eBitWarning(mV, u32 endCount) {
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if (endCount == 1) Console::Error("microVU%d Warning: Branch, E-bit, Branch! [%04x]", params mVU->index, xPC);
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microVUt(void) eBitWarning(mV) {
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if (mVUpBlock->pState.blockType == 1) Console::Error("microVU%d Warning: Branch, E-bit, Branch! [%04x]", params mVU->index, xPC);
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if (mVUpBlock->pState.blockType == 2) Console::Error("microVU%d Warning: Branch, Branch, Branch! [%04x]", params mVU->index, xPC);
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incPC(2);
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if (curI & _Ebit_) {
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DevCon::Status("microVU%d: E-bit in Branch delay slot! [%04x]", params mVU->index, xPC);
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@ -361,7 +362,7 @@ microVUr(void*) mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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mVUinfo.writeP = !mVU->p;
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if (branch >= 2) { mVUinfo.isEOB = 1; if (branch == 3) { mVUinfo.isBdelay = 1; } mVUcount++; branchWarning(mVU); break; }
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else if (branch == 1) { branch = 2; }
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if (mVUbranch) { mVUsetFlagInfo(mVU); eBitWarning(mVU, endCount); branch = 3; mVUbranch = 0; }
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if (mVUbranch) { mVUsetFlagInfo(mVU); eBitWarning(mVU); branch = 3; mVUbranch = 0; }
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incPC(1);
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}
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@ -385,11 +386,13 @@ microVUr(void*) mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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else { doSwapOp(mVU); }
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if (mVUinfo.doXGKICK) { mVU_XGKICK_DELAY(mVU, 1); }
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if (!doRegAlloc) { mVU->regAlloc->flushAll(); }
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if (!mVUinfo.isBdelay) { incPC(1); }
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if (_isBlock2) { mVUsetupRange(mVU, xPC, 0); normJumpCompile(mVU, mFC, 1); return thisPtr; }
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else if (!mVUinfo.isBdelay) { incPC(1); }
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else {
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mVUsetupRange(mVU, xPC, 0);
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mVUdebugNOW(1);
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switch (mVUbranch) {
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incPC(-3); // Go back to branch opcode
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switch (mVUlow.branch) {
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case 1: case 2: normBranch(mVU, mFC); return thisPtr; // B/BAL
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case 9: case 10: normJump (mVU, mFC); return thisPtr; // JR/JALR
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case 3: condBranch(mVU, mFC, Jcc_Equal); return thisPtr; // IBEQ
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@ -44,7 +44,7 @@ __declspec(align(16)) struct microRegInfo { // Ordered for Faster Compares
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u8 VI[16];
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regInfo VF[32];
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u8 flags; // clip x2 :: status x2
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u8 blockType; // 0 = Normal; 1 = Compile one instruction with E-bit termination
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u8 blockType; // 0 = Normal; 1 = Compile one instruction (E-bit End); 2 = Compile one instruction (Branch End)
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u8 padding[5]; // 160 bytes
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#if defined(_MSC_VER)
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};
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@ -107,6 +107,7 @@ struct microLowerOp {
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microVIreg VI_read[2]; // VI regs read by this instruction
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microConstInfo constJump; // Constant Reg Info for JR/JARL instructions
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u32 branch; // Branch Type (0 = Not a Branch, 1 = B. 2 = BAL, 3~8 = Conditional Branches, 9 = JALR, 10 = JR)
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bool evilBranch;// This instruction is a Branch in a Branch Delay Slot
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bool isNOP; // This instruction is a NOP
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bool isFSSET; // This instruction is a FSSET
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bool noWriteVF; // Don't write back the result of a lower op to VF reg if upper op writes to same reg (or if VF = 0)
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@ -1164,9 +1164,21 @@ void setBranchA(mP, int x, int _x_) {
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pass4 { if (_Imm11_ == 1 && !_x_) { return; } mVUbranch = x; }
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}
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void condEvilBranch(mV, int JMPcc) {
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using namespace x86Emitter;
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xCMP(ax, 0);
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xMOV(ptr32[&mVU->evilBranch], branchAddr);
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xForwardJump8 cJMP((JccComparisonType)JMPcc);
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incPC(-2); // Branch Not Taken
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xMOV(ptr32[&mVU->evilBranch], ((branchAddr+8) & (mVU->microMemSize-8)));
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incPC(2);
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cJMP.SetTarget();
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}
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mVUop(mVU_B) {
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setBranchA(mX, 1, 0);
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pass1 { mVUanalyzeNormBranch(mVU, 0, 0); }
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pass2 { if (mVUlow.evilBranch) { MOV32ItoM((uptr)&mVU->evilBranch, branchAddr); } }
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pass3 { mVUlog("B [<a href=\"#addr%04x\">%04x</a>]", branchAddr, branchAddr); }
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}
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@ -1176,76 +1188,93 @@ mVUop(mVU_BAL) {
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pass2 {
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MOV32ItoR(gprT1, bSaveAddr);
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mVUallocVIb(mVU, gprT1, _It_);
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if (mVUlow.evilBranch) { MOV32ItoM((uptr)&mVU->evilBranch, branchAddr); }
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}
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pass3 { mVUlog("BAL vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, branchAddr, branchAddr); }
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}
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mVUop(mVU_IBEQ) {
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using namespace x86Emitter;
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setBranchA(mX, 3, 0);
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pass1 { mVUanalyzeCondBranch2(mVU, _Is_, _It_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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if (mVUlow.memReadIt) XOR32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else { mVUallocVIa(mVU, gprT2, _It_); XOR32RtoR(gprT1, gprT2); }
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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if (!mVUlow.evilBranch) { MOV32RtoM((uptr)&mVU->branch, gprT1); }
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else { condEvilBranch(mVU, Jcc_Equal); }
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}
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pass3 { mVUlog("IBEQ vi%02d, vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, _Fs_, branchAddr, branchAddr); }
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}
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mVUop(mVU_IBGEZ) {
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using namespace x86Emitter;
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setBranchA(mX, 4, 0);
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pass1 { mVUanalyzeCondBranch1(mVU, _Is_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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if (!mVUlow.evilBranch) MOV32RtoM((uptr)&mVU->branch, gprT1);
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else condEvilBranch(mVU, Jcc_GreaterOrEqual);
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}
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pass3 { mVUlog("IBGEZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr, branchAddr); }
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}
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mVUop(mVU_IBGTZ) {
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using namespace x86Emitter;
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setBranchA(mX, 5, 0);
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pass1 { mVUanalyzeCondBranch1(mVU, _Is_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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if (!mVUlow.evilBranch) MOV32RtoM((uptr)&mVU->branch, gprT1);
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else condEvilBranch(mVU, Jcc_Greater);
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}
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pass3 { mVUlog("IBGTZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr, branchAddr); }
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}
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mVUop(mVU_IBLEZ) {
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using namespace x86Emitter;
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setBranchA(mX, 6, 0);
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pass1 { mVUanalyzeCondBranch1(mVU, _Is_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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if (!mVUlow.evilBranch) MOV32RtoM((uptr)&mVU->branch, gprT1);
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else condEvilBranch(mVU, Jcc_LessOrEqual);
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}
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pass3 { mVUlog("IBLEZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr, branchAddr); }
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}
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mVUop(mVU_IBLTZ) {
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using namespace x86Emitter;
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setBranchA(mX, 7, 0);
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pass1 { mVUanalyzeCondBranch1(mVU, _Is_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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if (!mVUlow.evilBranch) MOV32RtoM((uptr)&mVU->branch, gprT1);
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else condEvilBranch(mVU, Jcc_Less);
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}
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pass3 { mVUlog("IBLTZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr, branchAddr); }
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}
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mVUop(mVU_IBNE) {
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using namespace x86Emitter;
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setBranchA(mX, 8, 0);
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pass1 { mVUanalyzeCondBranch2(mVU, _Is_, _It_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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if (mVUlow.memReadIt) XOR32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else { mVUallocVIa(mVU, gprT2, _It_); XOR32RtoR(gprT1, gprT2); }
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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if (!mVUlow.evilBranch) { MOV32RtoM((uptr)&mVU->branch, gprT1); }
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else { condEvilBranch(mVU, Jcc_NotEqual); }
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}
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pass3 { mVUlog("IBNE vi%02d, vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, _Fs_, branchAddr, branchAddr); }
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}
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@ -1254,11 +1283,12 @@ mVUop(mVU_JR) {
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mVUbranch = 9;
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pass1 { mVUanalyzeJump(mVU, _Is_, 0, 0); }
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pass2 {
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if (!mVUlow.constJump.isValid) {
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if (!mVUlow.constJump.isValid || mVUlow.evilBranch) {
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mVUallocVIa(mVU, gprT1, _Is_);
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SHL32ItoR(gprT1, 3);
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AND32ItoR(gprT1, mVU->microMemSize - 8);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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if (!mVUlow.evilBranch) MOV32RtoM((uptr)&mVU->branch, gprT1);
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else MOV32RtoM((uptr)&mVU->evilBranch, gprT1);
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}
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}
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pass3 { mVUlog("JR [vi%02d]", _Fs_); }
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@ -1268,11 +1298,13 @@ mVUop(mVU_JALR) {
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mVUbranch = 10;
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pass1 { mVUanalyzeJump(mVU, _Is_, _It_, 1); }
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pass2 {
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if (!mVUlow.constJump.isValid) {
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if (!mVUlow.constJump.isValid || mVUlow.evilBranch) {
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mVUallocVIa(mVU, gprT1, _Is_);
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SHL32ItoR(gprT1, 3);
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AND32ItoR(gprT1, mVU->microMemSize - 8);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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if (!mVUlow.evilBranch) MOV32RtoM((uptr)&mVU->branch, gprT1);
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else MOV32RtoM((uptr)&mVU->evilBranch, gprT1);
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}
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MOV32ItoR(gprT1, bSaveAddr);
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mVUallocVIb(mVU, gprT1, _It_);
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@ -206,6 +206,7 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
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#define mFLAG mVUinfo.mFlag
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#define cFLAG mVUinfo.cFlag
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#define mVUrange mVUcurProg.ranges.range[mVUcurProg.ranges.total]
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#define _isBlock2 (mVUpBlock->pState.blockType == 2)
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#define xPC ((iPC / 2) * 8)
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#define curI ((u32*)mVU->regs->Micro)[iPC] //mVUcurProg.data[iPC]
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#define setCode() { mVU->code = curI; }
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Reference in New Issue