ShuriZma
/
pcsx2
mirror of https://github.com/PCSX2/pcsx2.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Since WriteLn is used for logging, and it automatically appends newlines, remove a bunch of legacy newlines from various logging functions. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@844 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-03-27 06:34:51 +00:00
parent 4ea9d9292f
commit 007c34a8b0
45 changed files with 917 additions and 911 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

119
pcsx2/CDVD.cpp
View File

@ -831,11 +831,11 @@ void mechaDecryptBytes( u32 madr, int size )
int cdvdReadSector() {
s32 bcr;
CDR_LOG("SECTOR %d (BCR %x;%x)\n", cdvd.Sector, HW_DMA3_BCR_H16, HW_DMA3_BCR_L16);
CDR_LOG("SECTOR %d (BCR %x;%x)", cdvd.Sector, HW_DMA3_BCR_H16, HW_DMA3_BCR_L16);
bcr = (HW_DMA3_BCR_H16 * HW_DMA3_BCR_L16) *4;
if (bcr < cdvd.BlockSize) {
CDR_LOG( "READBLOCK: bcr < cdvd.BlockSize; %x < %x\n", bcr, cdvd.BlockSize );
CDR_LOG( "READBLOCK: bcr < cdvd.BlockSize; %x < %x", bcr, cdvd.BlockSize );
if (HW_DMA3_CHCR & 0x01000000) {
HW_DMA3_CHCR &= ~0x01000000;
psxDmaInterrupt(3);
@ -907,8 +907,7 @@ int cdvdReadSector() {
}
// decrypt sector's bytes
if( cdvd.decSet )
mechaDecryptBytes( HW_DMA3_MADR, cdvd.BlockSize );
if( cdvd.decSet ) mechaDecryptBytes( HW_DMA3_MADR, cdvd.BlockSize );
// Added a clear after memory write .. never seemed to be necessary before but *should*
// be more correct. (air)
@ -980,7 +979,7 @@ __forceinline void cdvdReadInterrupt()
cdvd.Status = CDVD_STATUS_SEEK_COMPLETE;
cdvd.Sector = cdvd.SeekToSector;
CDR_LOG( "Cdvd Seek Complete > Scheduling block read interrupt at iopcycle=%8.8x.\n",
CDR_LOG( "Cdvd Seek Complete > Scheduling block read interrupt at iopcycle=%8.8x.",
psxRegs.cycle + cdvd.ReadTime );
CDVDREAD_INT(cdvd.ReadTime);
@ -1068,93 +1067,93 @@ void cdvdVsync() {
u8 cdvdRead04(void) { // NCOMMAND
CDR_LOG("cdvdRead04(NCMD) %x\n", cdvd.nCommand);
CDR_LOG("cdvdRead04(NCMD) %x", cdvd.nCommand);
return cdvd.nCommand;
}
u8 cdvdRead05(void) { // N-READY
CDR_LOG("cdvdRead05(NReady) %x\n", cdvd.Ready);
CDR_LOG("cdvdRead05(NReady) %x", cdvd.Ready);
return cdvd.Ready;
}
u8 cdvdRead06(void) { // ERROR
CDR_LOG("cdvdRead06(Error) %x\n", cdvd.Error);
CDR_LOG("cdvdRead06(Error) %x", cdvd.Error);
return cdvd.Error;
}
u8 cdvdRead07(void) { // BREAK
CDR_LOG("cdvdRead07(Break) %x\n", 0);
CDR_LOG("cdvdRead07(Break) %x", 0);
return 0;
}
u8 cdvdRead08(void) { // INTR_STAT
CDR_LOG("cdvdRead08(IntrReason) %x\n", cdvd.PwOff);
CDR_LOG("cdvdRead08(IntrReason) %x", cdvd.PwOff);
return cdvd.PwOff;
}
u8 cdvdRead0A(void) { // STATUS
CDR_LOG("cdvdRead0A(Status) %x\n", cdvd.Status);
CDR_LOG("cdvdRead0A(Status) %x", cdvd.Status);
return cdvd.Status;
}
u8 cdvdRead0B(void) { // TRAY-STATE (if tray has been opened)
u8 tray = cdvdGetTrayStatus();
CDR_LOG("cdvdRead0B(Tray) %x\n", tray);
CDR_LOG("cdvdRead0B(Tray) %x", tray);
return tray;
}
u8 cdvdRead0C(void) { // CRT MINUTE
CDR_LOG("cdvdRead0C(Min) %x\n", itob((u8)(cdvd.Sector/(60*75))));
CDR_LOG("cdvdRead0C(Min) %x", itob((u8)(cdvd.Sector/(60*75))));
return itob((u8)(cdvd.Sector/(60*75)));
}
u8 cdvdRead0D(void) { // CRT SECOND
CDR_LOG("cdvdRead0D(Sec) %x\n", itob((u8)((cdvd.Sector/75)%60)+2));
CDR_LOG("cdvdRead0D(Sec) %x", itob((u8)((cdvd.Sector/75)%60)+2));
return itob((u8)((cdvd.Sector/75)%60)+2);
}
u8 cdvdRead0E(void) { // CRT FRAME
CDR_LOG("cdvdRead0E(Frame) %x\n", itob((u8)(cdvd.Sector%75)));
CDR_LOG("cdvdRead0E(Frame) %x", itob((u8)(cdvd.Sector%75)));
return itob((u8)(cdvd.Sector%75));
}
u8 cdvdRead0F(void) // TYPE
{
CDR_LOG("cdvdRead0F(Disc Type) %x\n", cdvd.Type);
CDR_LOG("cdvdRead0F(Disc Type) %x", cdvd.Type);
cdvdGetDiskType();
return cdvd.Type;
}
u8 cdvdRead13(void) { // UNKNOWN
CDR_LOG("cdvdRead13(Unknown) %x\n", 4);
CDR_LOG("cdvdRead13(Unknown) %x", 4);
return 4;
}
u8 cdvdRead15(void) { // RSV
CDR_LOG("cdvdRead15(RSV)\n");
CDR_LOG("cdvdRead15(RSV)");
return 0x01; // | 0x80 for ATAPI mode
}
u8 cdvdRead16(void) { // SCOMMAND
CDR_LOG("cdvdRead16(SCMD) %x\n", cdvd.sCommand);
CDR_LOG("cdvdRead16(SCMD) %x", cdvd.sCommand);
return cdvd.sCommand;
}
u8 cdvdRead17(void) { // SREADY
CDR_LOG("cdvdRead17(SReady) %x\n", cdvd.sDataIn);
CDR_LOG("cdvdRead17(SReady) %x", cdvd.sDataIn);
return cdvd.sDataIn;
}
@ -1169,54 +1168,54 @@ u8 cdvdRead18(void) { // SDATAOUT
ret = cdvd.Result[cdvd.ResultP-1];
}
}
CDR_LOG("cdvdRead18(SDataOut) %x (ResultC=%d, ResultP=%d)\n", ret, cdvd.ResultC, cdvd.ResultP);
CDR_LOG("cdvdRead18(SDataOut) %x (ResultC=%d, ResultP=%d)", ret, cdvd.ResultC, cdvd.ResultP);
return ret;
}
u8 cdvdRead20(void) {
CDR_LOG("cdvdRead20(Key0) %x\n", cdvd.Key[0]);
CDR_LOG("cdvdRead20(Key0) %x", cdvd.Key[0]);
return cdvd.Key[0];
}
u8 cdvdRead21(void) {
CDR_LOG("cdvdRead21(Key1) %x\n", cdvd.Key[1]);
CDR_LOG("cdvdRead21(Key1) %x", cdvd.Key[1]);
return cdvd.Key[1];
}
u8 cdvdRead22(void) {
CDR_LOG("cdvdRead22(Key2) %x\n", cdvd.Key[2]);
CDR_LOG("cdvdRead22(Key2) %x", cdvd.Key[2]);
return cdvd.Key[2];
}
u8 cdvdRead23(void) {
CDR_LOG("cdvdRead23(Key3) %x\n", cdvd.Key[3]);
CDR_LOG("cdvdRead23(Key3) %x", cdvd.Key[3]);
return cdvd.Key[3];
}
u8 cdvdRead24(void) {
CDR_LOG("cdvdRead24(Key4) %x\n", cdvd.Key[4]);
CDR_LOG("cdvdRead24(Key4) %x", cdvd.Key[4]);
return cdvd.Key[4];
}
u8 cdvdRead28(void) {
CDR_LOG("cdvdRead28(Key5) %x\n", cdvd.Key[5]);
CDR_LOG("cdvdRead28(Key5) %x", cdvd.Key[5]);
return cdvd.Key[5];
}
u8 cdvdRead29(void) {
CDR_LOG("cdvdRead29(Key6) %x\n", cdvd.Key[6]);
CDR_LOG("cdvdRead29(Key6) %x", cdvd.Key[6]);
return cdvd.Key[6];
}
u8 cdvdRead2A(void) {
CDR_LOG("cdvdRead2A(Key7) %x\n", cdvd.Key[7]);
CDR_LOG("cdvdRead2A(Key7) %x", cdvd.Key[7]);
return cdvd.Key[7];
}
@ -1228,55 +1227,55 @@ u8 cdvdRead2B(void) {
}
u8 cdvdRead2C(void) {
CDR_LOG("cdvdRead2C(Key9) %x\n", cdvd.Key[9]);
CDR_LOG("cdvdRead2C(Key9) %x", cdvd.Key[9]);
return cdvd.Key[9];
}
u8 cdvdRead30(void) {
CDR_LOG("cdvdRead30(Key10) %x\n", cdvd.Key[10]);
CDR_LOG("cdvdRead30(Key10) %x", cdvd.Key[10]);
return cdvd.Key[10];
}
u8 cdvdRead31(void) {
CDR_LOG("cdvdRead31(Key11) %x\n", cdvd.Key[11]);
CDR_LOG("cdvdRead31(Key11) %x", cdvd.Key[11]);
return cdvd.Key[11];
}
u8 cdvdRead32(void) {
CDR_LOG("cdvdRead32(Key12) %x\n", cdvd.Key[12]);
CDR_LOG("cdvdRead32(Key12) %x", cdvd.Key[12]);
return cdvd.Key[12];
}
u8 cdvdRead33(void) {
CDR_LOG("cdvdRead33(Key13) %x\n", cdvd.Key[13]);
CDR_LOG("cdvdRead33(Key13) %x", cdvd.Key[13]);
return cdvd.Key[13];
}
u8 cdvdRead34(void) {
CDR_LOG("cdvdRead34(Key14) %x\n", cdvd.Key[14]);
CDR_LOG("cdvdRead34(Key14) %x", cdvd.Key[14]);
return cdvd.Key[14];
}
u8 cdvdRead38(void) { // valid parts of key data (first and last are valid)
CDR_LOG("cdvdRead38(KeysValid) %x\n", cdvd.Key[15]);
CDR_LOG("cdvdRead38(KeysValid) %x", cdvd.Key[15]);
return cdvd.Key[15];
}
u8 cdvdRead39(void) { // KEY-XOR
CDR_LOG("cdvdRead39(KeyXor) %x\n", cdvd.KeyXor);
CDR_LOG("cdvdRead39(KeyXor) %x", cdvd.KeyXor);
return cdvd.KeyXor;
}
u8 cdvdRead3A(void) { // DEC_SET
CDR_LOG("cdvdRead3A(DecSet) %x\n", cdvd.decSet);
CDR_LOG("cdvdRead3A(DecSet) %x", cdvd.decSet);
Console::WriteLn("DecSet Read: %02X", params cdvd.decSet);
return cdvd.decSet;
@ -1298,7 +1297,7 @@ static uint cdvdStartSeek( uint newsector, CDVD_MODE_TYPE mode )
if( !cdvd.Spinning )
{
CDR_LOG( "CdSpinUp > Simulating CdRom Spinup Time, and seek to sector %d\n", cdvd.SeekToSector );
CDR_LOG( "CdSpinUp > Simulating CdRom Spinup Time, and seek to sector %d", cdvd.SeekToSector );
seektime = PSXCLK / 3; // 333ms delay
cdvd.Spinning = true;
}
@ -1309,18 +1308,18 @@ static uint cdvdStartSeek( uint newsector, CDVD_MODE_TYPE mode )
if( delta >= tbl_FastSeekDelta[mode] )
{
// Full Seek
CDR_LOG( "CdSeek Begin > to sector %d, from %d - delta=%d [FULL]\n", cdvd.SeekToSector, cdvd.Sector, delta );
CDR_LOG( "CdSeek Begin > to sector %d, from %d - delta=%d [FULL]", cdvd.SeekToSector, cdvd.Sector, delta );
seektime = Cdvd_FullSeek_Cycles;
}
else
{
CDR_LOG( "CdSeek Begin > to sector %d, from %d - delta=%d [FAST]\n", cdvd.SeekToSector, cdvd.Sector, delta );
CDR_LOG( "CdSeek Begin > to sector %d, from %d - delta=%d [FAST]", cdvd.SeekToSector, cdvd.Sector, delta );
seektime = Cdvd_FastSeek_Cycles;
}
}
else
{
CDR_LOG( "CdSeek Begin > Contiguous block without seek - delta=%d sectors\n", delta );
CDR_LOG( "CdSeek Begin > Contiguous block without seek - delta=%d sectors", delta );
// seektime is the time it takes to read to the destination block:
seektime = delta * cdvd.ReadTime;
@ -1342,7 +1341,7 @@ static uint cdvdStartSeek( uint newsector, CDVD_MODE_TYPE mode )
}
void cdvdWrite04(u8 rt) { // NCOMMAND
CDR_LOG("cdvdWrite04: NCMD %s (%x) (ParamP = %x)\n", nCmdName[rt], rt, cdvd.ParamP);
CDR_LOG("cdvdWrite04: NCMD %s (%x) (ParamP = %x)", nCmdName[rt], rt, cdvd.ParamP);
cdvd.nCommand = rt;
cdvd.Status = CDVD_STATUS_NONE;
@ -1394,7 +1393,7 @@ void cdvdWrite04(u8 rt) { // NCOMMAND
case 0: default: cdvd.ReadMode = CDVD_MODE_2048; cdvd.BlockSize = 2048; break;
}
CDR_LOG( "CdRead > startSector=%d, nSectors=%d, RetryCnt=%x, Speed=%x(%x), ReadMode=%x(%x) (1074=%x)\n",
CDR_LOG( "CdRead > startSector=%d, nSectors=%d, RetryCnt=%x, Speed=%x(%x), ReadMode=%x(%x) (1074=%x)",
cdvd.Sector, cdvd.nSectors, cdvd.RetryCnt, cdvd.Speed, cdvd.Param[9], cdvd.ReadMode, cdvd.Param[10], psxHu32(0x1074));
if( Config.cdvdPrint )
@ -1435,7 +1434,7 @@ void cdvdWrite04(u8 rt) { // NCOMMAND
case 0: cdvd.ReadMode = CDVD_MODE_2352; cdvd.BlockSize = 2352; break;
}
CDR_LOG( "CdReadCDDA > startSector=%d, nSectors=%d, RetryCnt=%x, Speed=%xx(%x), ReadMode=%x(%x) (1074=%x)\n",
CDR_LOG( "CdReadCDDA > startSector=%d, nSectors=%d, RetryCnt=%x, Speed=%xx(%x), ReadMode=%x(%x) (1074=%x)",
cdvd.Sector, cdvd.nSectors, cdvd.RetryCnt, cdvd.Speed, cdvd.Param[9], cdvd.ReadMode, cdvd.Param[10], psxHu32(0x1074));
if( Config.cdvdPrint )
@ -1466,7 +1465,7 @@ void cdvdWrite04(u8 rt) { // NCOMMAND
cdvd.ReadMode = CDVD_MODE_2048;
cdvd.BlockSize = 2064; // Why oh why was it 2064
CDR_LOG( "DvdRead > startSector=%d, nSectors=%d, RetryCnt=%x, Speed=%x(%x), ReadMode=%x(%x) (1074=%x)\n",
CDR_LOG( "DvdRead > startSector=%d, nSectors=%d, RetryCnt=%x, Speed=%x(%x), ReadMode=%x(%x) (1074=%x)",
cdvd.Sector, cdvd.nSectors, cdvd.RetryCnt, cdvd.Speed, cdvd.Param[9], cdvd.ReadMode, cdvd.Param[10], psxHu32(0x1074));
if( Config.cdvdPrint )
@ -1505,7 +1504,7 @@ void cdvdWrite04(u8 rt) { // NCOMMAND
u8 arg0 = cdvd.Param[0];
u16 arg1 = cdvd.Param[1] | (cdvd.Param[2]<<8);
u32 arg2 = cdvd.Param[3] | (cdvd.Param[4]<<8) | (cdvd.Param[5]<<16) | (cdvd.Param[6]<<24);
DevCon::WriteLn("cdvdReadKey(%d, %d, %d)\n", params arg0, arg1, arg2);
DevCon::WriteLn("cdvdReadKey(%d, %d, %d)", params arg0, arg1, arg2);
cdvdReadKey(arg0, arg1, arg2, cdvd.Key);
cdvd.KeyXor = 0x00;
cdvdSetIrq();
@ -1527,7 +1526,7 @@ void cdvdWrite04(u8 rt) { // NCOMMAND
}
void cdvdWrite05(u8 rt) { // NDATAIN
CDR_LOG("cdvdWrite05(NDataIn) %x\n", rt);
CDR_LOG("cdvdWrite05(NDataIn) %x", rt);
if (cdvd.ParamP < 32) {
cdvd.Param[cdvd.ParamP++] = rt;
@ -1536,13 +1535,13 @@ void cdvdWrite05(u8 rt) { // NDATAIN
}
void cdvdWrite06(u8 rt) { // HOWTO
CDR_LOG("cdvdWrite06(HowTo) %x\n", rt);
CDR_LOG("cdvdWrite06(HowTo) %x", rt);
cdvd.HowTo = rt;
}
void cdvdWrite07(u8 rt) // BREAK
{
CDR_LOG("cdvdWrite07(Break) %x\n", rt);
CDR_LOG("cdvdWrite07(Break) %x", rt);
// If we're already in a Ready state or already Breaking, then do nothing:
if( cdvd.Ready != 0 || cdvd.Action == cdvdAction_Break )
@ -1566,24 +1565,24 @@ void cdvdWrite07(u8 rt) // BREAK
}
void cdvdWrite08(u8 rt) { // INTR_STAT
CDR_LOG("cdvdWrite08(IntrReason) = ACK(%x)\n", rt);
CDR_LOG("cdvdWrite08(IntrReason) = ACK(%x)", rt);
cdvd.PwOff &= ~rt;
}
void cdvdWrite0A(u8 rt) { // STATUS
CDR_LOG("cdvdWrite0A(Status) %x\n", rt);
CDR_LOG("cdvdWrite0A(Status) %x", rt);
}
void cdvdWrite0F(u8 rt) { // TYPE
CDR_LOG("cdvdWrite0F(Type) %x\n", rt);
DevCon::WriteLn("*PCSX2*: CDVD TYPE %x\n", params rt);
CDR_LOG("cdvdWrite0F(Type) %x", rt);
DevCon::WriteLn("*PCSX2*: CDVD TYPE %x", params rt);
}
void cdvdWrite14(u8 rt) { // PS1 MODE??
u32 cycle = psxRegs.cycle;
if (rt == 0xFE) Console::Notice("*PCSX2*: go PS1 mode DISC SPEED = FAST\n");
else Console::Notice("*PCSX2*: go PS1 mode DISC SPEED = %dX\n", params rt);
if (rt == 0xFE) Console::Notice("*PCSX2*: go PS1 mode DISC SPEED = FAST");
else Console::Notice("*PCSX2*: go PS1 mode DISC SPEED = %dX", params rt);
psxReset();
psxHu32(0x1f801450) = 0x8;
@ -1599,7 +1598,7 @@ void cdvdWrite16(u8 rt) // SCOMMAND
int address;
u8 tmp;
CDR_LOG("cdvdWrite16: SCMD %s (%x) (ParamP = %x)\n", sCmdName[rt], rt, cdvd.ParamP);
CDR_LOG("cdvdWrite16: SCMD %s (%x) (ParamP = %x)", sCmdName[rt], rt, cdvd.ParamP);
cdvd.sCommand = rt;
switch (rt) {
@ -2153,7 +2152,7 @@ fail_pol_cal:
}
void cdvdWrite17(u8 rt) { // SDATAIN
CDR_LOG("cdvdWrite17(SDataIn) %x\n", rt);
CDR_LOG("cdvdWrite17(SDataIn) %x", rt);
if (cdvd.ParamP < 32) {
cdvd.Param[cdvd.ParamP++] = rt;
@ -2162,12 +2161,12 @@ void cdvdWrite17(u8 rt) { // SDATAIN
}
void cdvdWrite18(u8 rt) { // SDATAOUT
CDR_LOG("cdvdWrite18(SDataOut) %x\n", rt);
CDR_LOG("cdvdWrite18(SDataOut) %x", rt);
Console::WriteLn("*PCSX2* SDATAOUT");
}
void cdvdWrite3A(u8 rt) { // DEC-SET
CDR_LOG("cdvdWrite3A(DecSet) %x\n", rt);
CDR_LOG("cdvdWrite3A(DecSet) %x", rt);
cdvd.decSet = rt;
Console::WriteLn("DecSet Write: %02X", params cdvd.decSet);
}

26
pcsx2/CDVDiso.cpp
View File

@ -295,13 +295,13 @@ int CDVD_findfile(const char* fname, TocEntry* tocEntry){
// Find the TOC for a specific directory
if (CDVD_GetVolumeDescriptor() != TRUE){
RPC_LOG("Could not get CD Volume Descriptor\n");
RPC_LOG("Could not get CD Volume Descriptor");
return -1;
}
// Read the TOC of the root directory
if (CdRead(CDVolDesc.rootToc.tocLBA,1,toc,&cdReadMode) != TRUE){
RPC_LOG("Couldn't Read from CD !\n");
RPC_LOG("Couldn't Read from CD !");
return -1;
}
//CdSync(0x00);
@ -422,7 +422,7 @@ int CDVD_findfile(const char* fname, TocEntry* tocEntry){
tocEntryPointer = (dirTocEntry*)((char*)tocEntryPointer + tocEntryPointer->length);
}
RPC_LOG("[RPC:cdvd] findfile: found dir, now looking for file\n");
RPC_LOG("[RPC:cdvd] findfile: found dir, now looking for file");
tocEntryPointer = (dirTocEntry*)toc;
@ -502,15 +502,15 @@ int CDVD_GetDir_RPC_request(char* pathname, char* extensions, unsigned int inc_d
// Find the TOC for a specific directory
if (CDVD_GetVolumeDescriptor() != TRUE){
RPC_LOG("[RPC:cdvd] Could not get CD Volume Descriptor\n");
RPC_LOG("[RPC:cdvd] Could not get CD Volume Descriptor");
return -1;
}
RPC_LOG("[RPC:cdvd] Getting Directory Listing for: \"%s\"\n", pathname);
RPC_LOG("[RPC:cdvd] Getting Directory Listing for: \"%s\"", pathname);
// Read the TOC of the root directory
if (CdRead(CDVolDesc.rootToc.tocLBA,1,toc,&cdReadMode) != TRUE){
RPC_LOG("[RPC: ] Couldn't Read from CD !\n");
RPC_LOG("[RPC: ] Couldn't Read from CD !");
return -1;
}
//CdSync(0x00);
@ -551,7 +551,7 @@ int CDVD_GetDir_RPC_request(char* pathname, char* extensions, unsigned int inc_d
current_sector++;
if (CdRead(current_sector,1,toc,&cdReadMode) != TRUE){
RPC_LOG("[RPC: ] Couldn't Read from CD !\n");
RPC_LOG("[RPC: ] Couldn't Read from CD !");
return -1;
}
@ -573,8 +573,8 @@ int CDVD_GetDir_RPC_request(char* pathname, char* extensions, unsigned int inc_d
if (strcmp(dirname,localTocEntry.filename) == 0){
// if the name matches then we've found the directory
found_dir = TRUE;
RPC_LOG("[RPC: ] Found directory %s in subdir at sector %d\n",dirname,current_sector);
RPC_LOG("[RPC: ] LBA of found subdirectory = %d\n",localTocEntry.fileLBA);
RPC_LOG("[RPC: ] Found directory %s in subdir at sector %d",dirname,current_sector);
RPC_LOG("[RPC: ] LBA of found subdirectory = %d",localTocEntry.fileLBA);
break;
}
@ -593,7 +593,7 @@ int CDVD_GetDir_RPC_request(char* pathname, char* extensions, unsigned int inc_d
// Read the TOC of the found subdirectory
if (CdRead(localTocEntry.fileLBA,1,toc,&cdReadMode) != TRUE){
RPC_LOG("[RPC: ] Couldn't Read from CD !\n");
RPC_LOG("[RPC: ] Couldn't Read from CD !");
return -1;
}
//CdSync(0x00);
@ -645,7 +645,7 @@ int CDVD_GetDir_RPC_request(char* pathname, char* extensions, unsigned int inc_d
getDirTocData.current_sector++;
if (CdRead(getDirTocData.current_sector,1,toc,&cdReadMode) != TRUE){
RPC_LOG("[RPC: ] Couldn't Read from CD !\n");
RPC_LOG("[RPC: ] Couldn't Read from CD !");
return -1;
}
//CdSync(0x00);
@ -710,7 +710,7 @@ int CDVD_GetDir_RPC_get_entries(TocEntry tocEntry[], int req_entries){
dirTocEntry* tocEntryPointer;
if (CdRead(getDirTocData.current_sector,1,toc,&cdReadMode) != TRUE){
RPC_LOG("[RPC:cdvd] Couldn't Read from CD !\n");
RPC_LOG("[RPC:cdvd] Couldn't Read from CD !");
return -1;
}
//CdSync(0x00);
@ -741,7 +741,7 @@ int CDVD_GetDir_RPC_get_entries(TocEntry tocEntry[], int req_entries){
getDirTocData.current_sector++;
if (CdRead(getDirTocData.current_sector,1,toc,&cdReadMode) != TRUE){
RPC_LOG("[RPC:cdvd] Couldn't Read from CD !\n");
RPC_LOG("[RPC:cdvd] Couldn't Read from CD !");
return -1;
}
//CdSync(0x00);

32
pcsx2/CDVDisodrv.cpp
View File

@ -52,9 +52,9 @@ void CDVDFS_init(){
if (inited) return;//might change in the future as a param; forceInit/Reset
RPC_LOG("[CDVDisodrv:init] CDVD Filesystem v1.00\n");
RPC_LOG("[CDVDisodrv ] \tby A.Lee (aka Hiryu) & Nicholas Van Veen (aka Sjeep)\n");
RPC_LOG("[CDVDisodrv ] Initializing '%s' file driver.\n", "cdfs");
RPC_LOG("[CDVDisodrv:init] CDVD Filesystem v1.00");
RPC_LOG("[CDVDisodrv ] \tby A.Lee (aka Hiryu) & Nicholas Van Veen (aka Sjeep)");
RPC_LOG("[CDVDisodrv ] Initializing '%s' file driver.", "cdfs");
//CdInit(0); already called by plugin loading system ;)
@ -92,13 +92,13 @@ int CDVDFS_open(const char *name, int mode){
fd_used[j] = 1;
files_open++;
RPC_LOG("[CDVDisodrv:open] internal fd=%d\n", j);
RPC_LOG("[CDVDisodrv:open] internal fd=%d", j);
fd_table[j].fileSize = tocEntry.fileSize;
fd_table[j].LBA = tocEntry.fileLBA;
fd_table[j].filePos = 0;
RPC_LOG("[CDVDisodrv ] tocEntry.fileSize = %d\n",tocEntry.fileSize);
RPC_LOG("[CDVDisodrv ] tocEntry.fileSize = %d",tocEntry.fileSize);
return j;
}
@ -109,7 +109,7 @@ int CDVDFS_open(const char *name, int mode){
int CDVDFS_lseek(int fd, int offset, int whence){
if ((fd >= 16) || (fd_used[fd]==0)){
RPC_LOG("[CDVDisodrv:lseek] ERROR: File does not appear to be open!\n");
RPC_LOG("[CDVDisodrv:lseek] ERROR: File does not appear to be open!");
return -1;
}
@ -155,7 +155,7 @@ int CDVDFS_read( int fd, char *buffer, int size ){
int ssize=0, asize, esize;
if ((fd >= 16) || (fd_used[fd]==0)){
RPC_LOG("[CDVDisodrv:read] ERROR: File does not appear to be open!\n");
RPC_LOG("[CDVDisodrv:read] ERROR: File does not appear to be open!");
return -1;
}
@ -181,22 +181,22 @@ int CDVDFS_read( int fd, char *buffer, int size ){
esector=asector + (asize >> 11);
size += ssize;
RPC_LOG("[CDVDisodrv:read] read sectors 0x%08X to 0x%08X\n", ssector, esector-(esize==0));
RPC_LOG("[CDVDisodrv:read] read sectors 0x%08X to 0x%08X", ssector, esector-(esize==0));
if (ssize){
if (CdRead(ssector, 1, lb, &cdReadMode) != TRUE){
RPC_LOG("[CDVDisodrv: ] Couldn't Read from file for some reason\n");
RPC_LOG("[CDVDisodrv: ] Couldn't Read from file for some reason");
return 0;
}
memcpy_fast(buffer, lb + off_sector, ssize);
}
if (asize) if (CdRead(asector, asize >> 11, buffer+ssize, &cdReadMode) != TRUE){
RPC_LOG("[CDVDisodrv: ] Couldn't Read from file for some reason\n");
RPC_LOG("[CDVDisodrv: ] Couldn't Read from file for some reason");
return 0;
}
if (esize){
if (CdRead(esector, 1, lb, &cdReadMode) != TRUE){
RPC_LOG("[CDVDisodrv: ] Couldn't Read from file for some reason\n");
RPC_LOG("[CDVDisodrv: ] Couldn't Read from file for some reason");
return 0;
}
memcpy_fast(buffer+ssize+asize, lb, esize);
@ -207,13 +207,13 @@ int CDVDFS_read( int fd, char *buffer, int size ){
off_sector = (fd_table[fd].filePos & 0x7FF);
num_sectors = ((off_sector + size) >> 11) + 1;
RPC_LOG("[CDVDisodrv:read] read sectors 0x%08X to 0x%08X\n",start_sector,start_sector+num_sectors);
RPC_LOG("[CDVDisodrv:read] read sectors 0x%08X to 0x%08X",start_sector,start_sector+num_sectors);
// Read the data (we only ever get 16KB max request at once)
if (CdRead(start_sector, num_sectors, local_buffer, &cdReadMode) != TRUE){
//RPC_LOG("sector = %d, start sector = %d\n",sector,start_sector);
RPC_LOG("[CDVDisodrv: ] Couldn't Read from file for some reason\n");
//RPC_LOG("sector = %d, start sector = %d",sector,start_sector);
RPC_LOG("[CDVDisodrv: ] Couldn't Read from file for some reason");
return 0;
}
//CdSync(0); hm, a wait function maybe...
@ -242,10 +242,10 @@ int CDVDFS_write( int fd, char * buffer, int size ){
int CDVDFS_close( int fd){
if ((fd >= 16) || (fd_used[fd]==0)){
RPC_LOG("[CDVDisodrv:close] ERROR: File does not appear to be open!\n");
RPC_LOG("[CDVDisodrv:close] ERROR: File does not appear to be open!");
return -1;
}
RPC_LOG("[CDVDisodrv:close] internal fd %d\n", fd);
RPC_LOG("[CDVDisodrv:close] internal fd %d", fd);
fd_used[fd] = 0;
files_open--;

12
pcsx2/COP0.cpp
View File

@ -306,7 +306,7 @@ void MFC0()
{
// Note on _Rd_ Condition 9: CP0.Count should be updated even if _Rt_ is 0.
if( (_Rd_ != 9) && !_Rt_ ) return;
if(_Rd_ != 9) { COP0_LOG("%s\n", disR5900Current.getCString() ); }
if(_Rd_ != 9) { COP0_LOG("%s", disR5900Current.getCString() ); }
//if(bExecBIOS == FALSE && _Rd_ == 25) Console::WriteLn("MFC0 _Rd_ %x = %x", params _Rd_, cpuRegs.CP0.r[_Rd_]);
switch (_Rd_)
@ -416,12 +416,12 @@ int CPCOND0() {
void BC0F() {
BC0(== 0);
COP0_LOG( "COP0 > BC0F\n" );
COP0_LOG( "COP0 > BC0F" );
}
void BC0T() {
BC0(== 1);
COP0_LOG( "COP0 > BC0T\n" );
COP0_LOG( "COP0 > BC0T" );
}
#define BC0L(cond) \
@ -431,12 +431,12 @@ void BC0T() {
void BC0FL() {
BC0L(== 0);
COP0_LOG( "COP0 > BC0FL\n" );
COP0_LOG( "COP0 > BC0FL" );
}
void BC0TL() {
BC0L(== 1);
COP0_LOG( "COP0 > BCOTL\n" );
COP0_LOG( "COP0 > BCOTL" );
}
void TLBR() {
@ -446,7 +446,7 @@ void TLBR() {
int i = cpuRegs.CP0.n.Index&0x1f;
COP0_LOG("COP0 > TLBR\n");
COP0_LOG("COP0 > TLBR");
cpuRegs.CP0.n.PageMask = tlb[i].PageMask;
cpuRegs.CP0.n.EntryHi = tlb[i].EntryHi&~(tlb[i].PageMask|0x1f00);
cpuRegs.CP0.n.EntryLo0 = (tlb[i].EntryLo0&~1)|((tlb[i].EntryHi>>12)&1);

28
pcsx2/Cache.cpp
View File

@ -101,7 +101,7 @@ void writeCache8(u32 mem, u8 value) {
int i, number;
i = getFreeCache(mem,1,&number);
// CACHE_LOG("writeCache8 %8.8x adding to %d, way %d, value %x\n", mem, i,number,value);
// CACHE_LOG("writeCache8 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
pCache[i].data[number][(mem>>4) & 0x3].b8._8[(mem&0xf)] = value;
}
@ -110,7 +110,7 @@ void writeCache16(u32 mem, u16 value) {
int i, number;
i = getFreeCache(mem,1,&number);
// CACHE_LOG("writeCache16 %8.8x adding to %d, way %d, value %x\n", mem, i,number,value);
// CACHE_LOG("writeCache16 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
*(u16*)(&pCache[i].data[number][(mem>>4) & 0x3].b8._8[(mem&0xf)]) = value;
}
@ -119,7 +119,7 @@ void writeCache32(u32 mem, u32 value) {
int i, number;
i = getFreeCache(mem,1,&number);
// CACHE_LOG("writeCache32 %8.8x adding to %d, way %d, value %x\n", mem, i,number,value);
// CACHE_LOG("writeCache32 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
*(u32*)(&pCache[i].data[number][(mem>>4) & 0x3].b8._8[(mem&0xf)]) = value;
}
@ -127,7 +127,7 @@ void writeCache64(u32 mem, u64 value) {
int i, number;
i = getFreeCache(mem,1,&number);
// CACHE_LOG("writeCache64 %8.8x adding to %d, way %d, value %x\n", mem, i,number,value);
// CACHE_LOG("writeCache64 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
*(u64*)(&pCache[i].data[number][(mem>>4) & 0x3].b8._8[(mem&0xf)]) = value;
}
@ -135,7 +135,7 @@ void writeCache128(u32 mem, u64 *value) {
int i, number;
i = getFreeCache(mem,1,&number);
// CACHE_LOG("writeCache128 %8.8x adding to %d\n", mem, i);
// CACHE_LOG("writeCache128 %8.8x adding to %d", mem, i);
((u64*)pCache[i].data[number][(mem>>4) & 0x3].b8._8)[0] = value[0];
((u64*)pCache[i].data[number][(mem>>4) & 0x3].b8._8)[1] = value[1];
}
@ -144,7 +144,7 @@ u8 *readCache(u32 mem) {
int i, number;
i = getFreeCache(mem,0,&number);
// CACHE_LOG("readCache %8.8x from %d, way %d\n", mem, i,number);
// CACHE_LOG("readCache %8.8x from %d, way %d", mem, i,number);
return pCache[i].data[number][(mem>>4) & 0x3].b8._8;
}
@ -180,7 +180,7 @@ void CACHE() {
return;
}
CACHE_LOG("CACHE DHIN addr %x, index %d, way %d, Flags %x\n",addr,index,way,pCache[index].tag[way] & 0x78);
CACHE_LOG("CACHE DHIN addr %x, index %d, way %d, Flags %x",addr,index,way,pCache[index].tag[way] & 0x78);
pCache[index].tag[way] &= ~(0x6F);
((u64*)pCache[index].data[way][0].b8._8)[0] = 0;
@ -216,7 +216,7 @@ void CACHE() {
return;
}
CACHE_LOG("CACHE DHWBIN addr %x, index %d, way %d, Flags %x\n",addr,index,way,pCache[index].tag[way] & 0x78);
CACHE_LOG("CACHE DHWBIN addr %x, index %d, way %d, Flags %x",addr,index,way,pCache[index].tag[way] & 0x78);
if(pCache[index].tag[way] & 0x60) // Valid Dirty
{
@ -266,7 +266,7 @@ void CACHE() {
{
return;
}
CACHE_LOG("CACHE DHWOIN addr %x, index %d, way %d, Flags %x\n",addr,index,way,pCache[index].tag[way] & 0x78);
CACHE_LOG("CACHE DHWOIN addr %x, index %d, way %d, Flags %x",addr,index,way,pCache[index].tag[way] & 0x78);
if(pCache[index].tag[way] & 0x60) // Valid Dirty
{
@ -311,7 +311,7 @@ void CACHE() {
u8 * out = pCache[index].data[way][(addr>>4) & 0x3].b8._8;
cpuRegs.CP0.r[28] = *(u32 *)(out+(addr&0xf));
CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x\n",addr,index,way,cpuRegs.CP0.r[28]);
CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x",addr,index,way,cpuRegs.CP0.r[28]);
break;
}
@ -323,7 +323,7 @@ void CACHE() {
cpuRegs.CP0.r[28] = 0;
cpuRegs.CP0.r[28] = pCache[index].tag[way];
CACHE_LOG("CACHE DXLTG addr %x, index %d, way %d, DATA %x\n",addr,index,way,cpuRegs.CP0.r[28]);
CACHE_LOG("CACHE DXLTG addr %x, index %d, way %d, DATA %x",addr,index,way,cpuRegs.CP0.r[28]);
break;
}
@ -334,7 +334,7 @@ void CACHE() {
//u8 * out = pCache[index].data[way][(addr>>4) & 0x3].b8._8;
*(u32*)(&pCache[index].data[way][(addr>>4) & 0x3].b8._8[(addr&0xf)]) = cpuRegs.CP0.r[28];
CACHE_LOG("CACHE DXSDT addr %x, index %d, way %d, DATA %x\n",addr,index,way,cpuRegs.CP0.r[28]);
CACHE_LOG("CACHE DXSDT addr %x, index %d, way %d, DATA %x",addr,index,way,cpuRegs.CP0.r[28]);
break;
}
@ -344,7 +344,7 @@ void CACHE() {
int way = addr & 0x1;
pCache[index].tag[way] = cpuRegs.CP0.r[28];
CACHE_LOG("CACHE DXSTG addr %x, index %d, way %d, DATA %x\n",addr,index,way,cpuRegs.CP0.r[28] & 0x6F);
CACHE_LOG("CACHE DXSTG addr %x, index %d, way %d, DATA %x",addr,index,way,cpuRegs.CP0.r[28] & 0x6F);
break;
}
@ -356,7 +356,7 @@ void CACHE() {
int way = addr & 0x1;
CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, Flags %x\n",addr,index,way,pCache[index].tag[way] & 0x78);
CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, Flags %x",addr,index,way,pCache[index].tag[way] & 0x78);
if(pCache[index].tag[way] & 0x60) // Dirty
{

30
pcsx2/CdRom.cpp
View File

@ -140,7 +140,7 @@ void ReadTrack() {
cdr.Prev[1] = itob(cdr.SetSector[1]);
cdr.Prev[2] = itob(cdr.SetSector[2]);
CDR_LOG("KEY *** %x:%x:%x\n", cdr.Prev[0], cdr.Prev[1], cdr.Prev[2]);
CDR_LOG("KEY *** %x:%x:%x", cdr.Prev[0], cdr.Prev[1], cdr.Prev[2]);
cdr.RErr = CDVDreadTrack(MSFtoLSN(cdr.SetSector), CDVD_MODE_2352);
}
@ -529,7 +529,7 @@ void cdrReadInterrupt() {
memcpy_fast(cdr.Transfer, buf+12, 2340);
cdr.Stat = DataReady;
CDR_LOG(" %x:%x:%x\n", cdr.Transfer[0], cdr.Transfer[1], cdr.Transfer[2]);
CDR_LOG(" %x:%x:%x", cdr.Transfer[0], cdr.Transfer[1], cdr.Transfer[2]);
cdr.SetSector[2]++;
@ -545,7 +545,7 @@ void cdrReadInterrupt() {
cdr.Readed = 0;
if ((cdr.Transfer[4+2] & 0x80) && (cdr.Mode & 0x2)) { // EOF
CDR_LOG("AutoPausing Read\n");
CDR_LOG("AutoPausing Read");
AddIrqQueue(CdlPause, 0x800);
}
else {
@ -583,7 +583,7 @@ u8 cdrRead0(void) {
// what means the 0x10 and the 0x08 bits? i only saw it used by the bios
cdr.Ctrl|=0x18;
CDR_LOG("CD0 Read: %x\n", cdr.Ctrl);
CDR_LOG("CD0 Read: %x", cdr.Ctrl);
return psxHu8(0x1800) = cdr.Ctrl;
}
@ -593,7 +593,7 @@ cdrWrite0:
*/
void cdrWrite0(u8 rt) {
CDR_LOG("CD0 write: %x\n", rt);
CDR_LOG("CD0 write: %x", rt);
cdr.Ctrl = rt | (cdr.Ctrl & ~0x3);
@ -612,14 +612,14 @@ u8 cdrRead1(void) {
else
psxHu8(0x1801) = 0;
CDR_LOG("CD1 Read: %x\n", psxHu8(0x1801));
CDR_LOG("CD1 Read: %x", psxHu8(0x1801));
return psxHu8(0x1801);
}
void cdrWrite1(u8 rt) {
int i;
CDR_LOG("CD1 write: %x (%s)\n", rt, CmdName[rt]);
CDR_LOG("CD1 write: %x (%s)", rt, CmdName[rt]);
cdr.Cmd = rt;
cdr.OCUP = 0;
@ -744,7 +744,7 @@ void cdrWrite1(u8 rt) {
break;
case CdlSetmode:
CDR_LOG("Setmode %x\n", cdr.Param[0]);
CDR_LOG("Setmode %x", cdr.Param[0]);
cdr.Mode = cdr.Param[0];
cdr.Ctrl|= 0x80;
@ -839,12 +839,12 @@ u8 cdrRead2(void) {
ret = *cdr.pTransfer++;
}
CDR_LOG("CD2 Read: %x\n", ret);
CDR_LOG("CD2 Read: %x", ret);
return ret;
}
void cdrWrite2(u8 rt) {
CDR_LOG("CD2 write: %x\n", rt);
CDR_LOG("CD2 write: %x", rt);
if (cdr.Ctrl & 0x1) {
switch (rt) {
@ -877,12 +877,12 @@ u8 cdrRead3(void) {
psxHu8(0x1803) = 0xff;
} else psxHu8(0x1803) = 0;
CDR_LOG("CD3 Read: %x\n", psxHu8(0x1803));
CDR_LOG("CD3 Read: %x", psxHu8(0x1803));
return psxHu8(0x1803);
}
void cdrWrite3(u8 rt) {
CDR_LOG("CD3 write: %x\n", rt);
CDR_LOG("CD3 write: %x", rt);
if (rt == 0x07 && cdr.Ctrl & 0x1) {
cdr.Stat = 0;
@ -909,13 +909,13 @@ void cdrWrite3(u8 rt) {
void psxDma3(u32 madr, u32 bcr, u32 chcr) {
u32 cdsize;
CDR_LOG("*** DMA 3 *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
CDR_LOG("*** DMA 3 *** %lx addr = %lx size = %lx", chcr, madr, bcr);
switch (chcr) {
case 0x11000000:
case 0x11400100:
if (cdr.Readed == 0) {
CDR_LOG("*** DMA 3 *** NOT READY\n");
CDR_LOG("*** DMA 3 *** NOT READY");
return;
}
@ -930,7 +930,7 @@ void psxDma3(u32 madr, u32 bcr, u32 chcr) {
return;
default:
CDR_LOG("Unknown cddma %lx\n", chcr);
CDR_LOG("Unknown cddma %lx", chcr);
break;
}
HW_DMA3_CHCR &= ~0x01000000;

31
pcsx2/Counters.cpp
View File

@ -327,7 +327,7 @@ static __forceinline void frameLimit()
static __forceinline void VSyncStart(u32 sCycle)
{
EECNT_LOG( "///////// EE COUNTER VSYNC START \\\\\\\\\\\\\\\\\\\\ (frame: %d)\n", iFrame );
EECNT_LOG( "///////// EE COUNTER VSYNC START \\\\\\\\\\\\\\\\\\\\ (frame: %d)", iFrame );
vSyncDebugStuff( iFrame ); // EE Profiling and Debug code
if ((CSRw & 0x8)) GSCSRr|= 0x8;
@ -361,7 +361,7 @@ static __forceinline void VSyncStart(u32 sCycle)
static __forceinline void VSyncEnd(u32 sCycle)
{
EECNT_LOG( "///////// EE COUNTER VSYNC END \\\\\\\\\\\\\\\\\\\\ (frame: %d)\n", iFrame );
EECNT_LOG( "///////// EE COUNTER VSYNC END \\\\\\\\\\\\\\\\\\\\ (frame: %d)", iFrame );
iFrame++;
@ -471,7 +471,7 @@ static __forceinline void __fastcall _cpuTestTarget( int i )
if(counters[i].mode.TargetInterrupt) {
EECNT_LOG("EE Counter[%d] TARGET reached - mode=%x, count=%x, target=%x\n", i, counters[i].mode, counters[i].count, counters[i].target);
EECNT_LOG("EE Counter[%d] TARGET reached - mode=%x, count=%x, target=%x", i, counters[i].mode, counters[i].count, counters[i].target);
counters[i].mode.TargetReached = 1;
hwIntcIrq(counters[i].interrupt);
@ -489,7 +489,7 @@ static __forceinline void _cpuTestOverflow( int i )
if (counters[i].count <= 0xffff) return;
if (counters[i].mode.OverflowInterrupt) {
EECNT_LOG("EE Counter[%d] OVERFLOW - mode=%x, count=%x\n", i, counters[i].mode, counters[i].count);
EECNT_LOG("EE Counter[%d] OVERFLOW - mode=%x, count=%x", i, counters[i].mode, counters[i].count);
counters[i].mode.OverflowReached = 1;
hwIntcIrq(counters[i].interrupt);
}
@ -547,7 +547,7 @@ static void _rcntSetGate( int index )
if( !(counters[index].mode.GateSource == 0 && counters[index].mode.ClockSource == 3) )
{
EECNT_LOG( "EE Counter[%d] Using Gate! Source=%s, Mode=%d.\n",
EECNT_LOG( "EE Counter[%d] Using Gate! Source=%s, Mode=%d.",
index, counters[index].mode.GateSource ? "vblank" : "hblank", counters[index].mode.GateMode );
gates |= (1<<index);
@ -556,7 +556,7 @@ static void _rcntSetGate( int index )
return;
}
else
EECNT_LOG( "EE Counter[%d] GATE DISABLED because of hblank source.\n", index );
EECNT_LOG( "EE Counter[%d] GATE DISABLED because of hblank source.", index );
}
gates &= ~(1<<index);
@ -595,7 +595,7 @@ void __fastcall rcntStartGate(bool isVblank, u32 sCycle)
counters[i].mode.IsCounting = 1;
counters[i].sCycleT = sCycle;
EECNT_LOG("EE Counter[%d] %s StartGate Type0, count = %x\n",
EECNT_LOG("EE Counter[%d] %s StartGate Type0, count = %x",
isVblank ? "vblank" : "hblank", i, counters[i].count );
break;
@ -609,7 +609,7 @@ void __fastcall rcntStartGate(bool isVblank, u32 sCycle)
counters[i].count = 0;
counters[i].target &= 0xffff;
counters[i].sCycleT = sCycle;
EECNT_LOG("EE Counter[%d] %s StartGate Type%d, count = %x\n",
EECNT_LOG("EE Counter[%d] %s StartGate Type%d, count = %x",
isVblank ? "vblank" : "hblank", i, counters[i].mode.GateMode, counters[i].count );
break;
}
@ -642,7 +642,7 @@ void __fastcall rcntEndGate(bool isVblank , u32 sCycle)
counters[i].count = rcntRcount(i);
counters[i].mode.IsCounting = 0;
counters[i].sCycleT = sCycle;
EECNT_LOG("EE Counter[%d] %s EndGate Type0, count = %x\n",
EECNT_LOG("EE Counter[%d] %s EndGate Type0, count = %x",
isVblank ? "vblank" : "hblank", i, counters[i].count );
break;
@ -656,7 +656,7 @@ void __fastcall rcntEndGate(bool isVblank , u32 sCycle)
counters[i].count = 0;
counters[i].target &= 0xffff;
counters[i].sCycleT = sCycle;
EECNT_LOG("EE Counter[%d] %s EndGate Type%d, count = %x\n",
EECNT_LOG("EE Counter[%d] %s EndGate Type%d, count = %x",
isVblank ? "vblank" : "hblank", i, counters[i].mode.GateMode, counters[i].count );
break;
}
@ -683,7 +683,7 @@ void __fastcall rcntWmode(int index, u32 value)
counters[index].modeval &= ~(value & 0xc00); //Clear status flags, the ps2 only clears what is given in the value
counters[index].modeval = (counters[index].modeval & 0xc00) | (value & 0x3ff);
EECNT_LOG("EE Counter[%d] writeMode = %x passed value=%x\n", index, counters[index].modeval, value );
EECNT_LOG("EE Counter[%d] writeMode = %x passed value=%x", index, counters[index].modeval, value );
switch (counters[index].mode.ClockSource) { //Clock rate divisers *2, they use BUSCLK speed not PS2CLK
case 0: counters[index].rate = 2; break;
@ -698,7 +698,7 @@ void __fastcall rcntWmode(int index, u32 value)
void __fastcall rcntWcount(int index, u32 value)
{
EECNT_LOG("EE Counter[%d] writeCount = %x, oldcount=%x, target=%x\n", index, value, counters[index].count, counters[index].target );
EECNT_LOG("EE Counter[%d] writeCount = %x, oldcount=%x, target=%x", index, value, counters[index].count, counters[index].target );
counters[index].count = value & 0xffff;
@ -724,7 +724,7 @@ void __fastcall rcntWcount(int index, u32 value)
void __fastcall rcntWtarget(int index, u32 value)
{
EECNT_LOG("EE Counter[%d] writeTarget = %x\n", index, value);
EECNT_LOG("EE Counter[%d] writeTarget = %x", index, value);
counters[index].target = value & 0xffff;
@ -740,7 +740,7 @@ void __fastcall rcntWtarget(int index, u32 value)
void __fastcall rcntWhold(int index, u32 value)
{
EECNT_LOG("EE Counter[%d] Hold Write = %x\n", index, value);
EECNT_LOG("EE Counter[%d] Hold Write = %x", index, value);
counters[index].hold = value;
}
@ -754,7 +754,8 @@ u32 __fastcall rcntRcount(int index)
else
ret = counters[index].count;
EECNT_LOG("EE Counter[%d] readCount32 = %x\n", index, ret);
// Spams the Console.
EECNT_LOG("EE Counter[%d] readCount32 = %x", index, ret);
return ret;
}

58
pcsx2/Elfheader.cpp
View File

@ -278,17 +278,17 @@ struct ElfObject
}
ELF_LOG("\n");
ELF_LOG("version: %d\n",header.e_version);
ELF_LOG("entry: %08x\n",header.e_entry);
ELF_LOG("flags: %08x\n",header.e_flags);
ELF_LOG("eh size: %08x\n",header.e_ehsize);
ELF_LOG("ph off: %08x\n",header.e_phoff);
ELF_LOG("ph entsiz: %08x\n",header.e_phentsize);
ELF_LOG("ph num: %08x\n",header.e_phnum);
ELF_LOG("sh off: %08x\n",header.e_shoff);
ELF_LOG("sh entsiz: %08x\n",header.e_shentsize);
ELF_LOG("sh num: %08x\n",header.e_shnum);
ELF_LOG("sh strndx: %08x\n",header.e_shstrndx);
ELF_LOG("version: %d",header.e_version);
ELF_LOG("entry: %08x",header.e_entry);
ELF_LOG("flags: %08x",header.e_flags);
ELF_LOG("eh size: %08x",header.e_ehsize);
ELF_LOG("ph off: %08x",header.e_phoff);
ELF_LOG("ph entsiz: %08x",header.e_phentsize);
ELF_LOG("ph num: %08x",header.e_phnum);
ELF_LOG("sh off: %08x",header.e_shoff);
ELF_LOG("sh entsiz: %08x",header.e_shentsize);
ELF_LOG("sh num: %08x",header.e_shnum);
ELF_LOG("sh strndx: %08x",header.e_shstrndx);
ELF_LOG("\n");
}
@ -341,7 +341,7 @@ struct ElfObject
for( int i = 0 ; i < header.e_phnum ; i++ )
{
ELF_LOG( "Elf32 Program Header\n" );
ELF_LOG( "Elf32 Program Header" );
ELF_LOG( "type: " );
switch ( proghead[ i ].p_type ) {
@ -379,13 +379,13 @@ struct ElfObject
}
ELF_LOG("\n");
ELF_LOG("offset: %08x\n",(int)proghead[i].p_offset);
ELF_LOG("vaddr: %08x\n",(int)proghead[i].p_vaddr);
ELF_LOG("paddr: %08x\n",proghead[i].p_paddr);
ELF_LOG("file size: %08x\n",proghead[i].p_filesz);
ELF_LOG("mem size: %08x\n",proghead[i].p_memsz);
ELF_LOG("flags: %08x\n",proghead[i].p_flags);
ELF_LOG("palign: %08x\n",proghead[i].p_align);
ELF_LOG("offset: %08x",(int)proghead[i].p_offset);
ELF_LOG("vaddr: %08x",(int)proghead[i].p_vaddr);
ELF_LOG("paddr: %08x",proghead[i].p_paddr);
ELF_LOG("file size: %08x",proghead[i].p_filesz);
ELF_LOG("mem size: %08x",proghead[i].p_memsz);
ELF_LOG("flags: %08x",proghead[i].p_flags);
ELF_LOG("palign: %08x",proghead[i].p_align);
ELF_LOG("\n");
}
}
@ -424,14 +424,14 @@ struct ElfObject
}
ELF_LOG("\n");
ELF_LOG("flags: %08x\n", secthead[i].sh_flags);
ELF_LOG("addr: %08x\n", secthead[i].sh_addr);
ELF_LOG("offset: %08x\n", secthead[i].sh_offset);
ELF_LOG("size: %08x\n", secthead[i].sh_size);
ELF_LOG("link: %08x\n", secthead[i].sh_link);
ELF_LOG("info: %08x\n", secthead[i].sh_info);
ELF_LOG("addralign: %08x\n", secthead[i].sh_addralign);
ELF_LOG("entsize: %08x\n", secthead[i].sh_entsize);
ELF_LOG("flags: %08x", secthead[i].sh_flags);
ELF_LOG("addr: %08x", secthead[i].sh_addr);
ELF_LOG("offset: %08x", secthead[i].sh_offset);
ELF_LOG("size: %08x", secthead[i].sh_size);
ELF_LOG("link: %08x", secthead[i].sh_link);
ELF_LOG("info: %08x", secthead[i].sh_info);
ELF_LOG("addralign: %08x", secthead[i].sh_addralign);
ELF_LOG("entsize: %08x", secthead[i].sh_entsize);
// dump symbol table
if( secthead[ i ].sh_type == 0x02 )
@ -548,7 +548,7 @@ int loadElfFile(const char *filename)
elfobj.loadSectionHeaders();
cpuRegs.pc = elfobj.header.e_entry; //set pc to proper place
ELF_LOG( "PC set to: %8.8lx\n", cpuRegs.pc );
ELF_LOG( "PC set to: %8.8lx", cpuRegs.pc );
cpuRegs.GPR.n.sp.UL[0] = 0x81f00000;
cpuRegs.GPR.n.gp.UL[0] = 0x81f80000; // might not be 100% ok
@ -562,7 +562,7 @@ int loadElfFile(const char *filename)
}
ElfCRC = elfobj.GetCRC();
Console::Status( "loadElfFile: %s; CRC = %8.8X\n", params filename, ElfCRC);
Console::Status( "loadElfFile: %s; CRC = %8.8X", params filename, ElfCRC);
ElfApplyPatches();
LoadGameSpecificSettings();

14
pcsx2/FiFo.cpp
View File

@ -55,7 +55,7 @@ void __fastcall ReadFIFO_page_4(u32 mem, u64 *out)
{
jASSUME( (mem >= 0x10004000) && (mem < 0x10005000) );
VIF_LOG("ReadFIFO/VIF0 0x%08X\n", mem);
VIF_LOG("ReadFIFO/VIF0 0x%08X", mem);
//out[0] = psHu64(mem );
//out[1] = psHu64(mem+8);
@ -67,7 +67,7 @@ void __fastcall ReadFIFO_page_5(u32 mem, u64 *out)
{
jASSUME( (mem >= 0x10005000) && (mem < 0x10006000) );
VIF_LOG("ReadFIFO/VIF1, addr=0x%08X\n", mem);
VIF_LOG("ReadFIFO/VIF1, addr=0x%08X", mem);
if( vif1Regs->stat & (VIF1_STAT_INT|VIF1_STAT_VSS|VIF1_STAT_VIS|VIF1_STAT_VFS) )
DevCon::Notice( "Reading from vif1 fifo when stalled" );
@ -127,7 +127,7 @@ void __fastcall WriteFIFO_page_4(u32 mem, const mem128_t *value)
{
jASSUME( (mem >= 0x10004000) && (mem < 0x10005000) );
VIF_LOG("WriteFIFO/VIF0, addr=0x%08X\n", mem);
VIF_LOG("WriteFIFO/VIF0, addr=0x%08X", mem);
//psHu64(mem ) = value[0];
//psHu64(mem+8) = value[1];
@ -144,7 +144,7 @@ void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value)
{
jASSUME( (mem >= 0x10005000) && (mem < 0x10006000) );
VIF_LOG("WriteFIFO/VIF1, addr=0x%08X\n", mem);
VIF_LOG("WriteFIFO/VIF1, addr=0x%08X", mem);
//psHu64(mem ) = value[0];
//psHu64(mem+8) = value[1];
@ -165,7 +165,7 @@ void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value)
void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value)
{
jASSUME( (mem >= 0x10006000) && (mem < 0x10007000) );
GIF_LOG("WriteFIFO/GIF, addr=0x%08X\n", mem);
GIF_LOG("WriteFIFO/GIF, addr=0x%08X", mem);
//psHu64(mem ) = value[0];
//psHu64(mem+8) = value[1];
@ -197,7 +197,7 @@ void __fastcall WriteFIFO_page_7(u32 mem, const mem128_t *value)
// All addresses in this page map to 0x7000 and 0x7010:
mem &= 0x10;
IPU_LOG( "WriteFIFO/IPU, addr=0x%x\n", params mem );
IPU_LOG( "WriteFIFO/IPU, addr=0x%x", params mem );
if( mem == 0 )
{
@ -206,7 +206,7 @@ void __fastcall WriteFIFO_page_7(u32 mem, const mem128_t *value)
}
else
{
IPU_LOG("WriteFIFO IPU_in[%d] <- %8.8X_%8.8X_%8.8X_%8.8X\n",
IPU_LOG("WriteFIFO IPU_in[%d] <- %8.8X_%8.8X_%8.8X_%8.8X",
mem/16, ((u32*)value)[3], ((u32*)value)[2], ((u32*)value)[1], ((u32*)value)[0]);
//committing every 16 bytes

20
pcsx2/GS.cpp
View File

@ -366,7 +366,7 @@ __forceinline void gsWrite8(u32 mem, u8 value)
if( mtgsThread != NULL )
mtgsThread->SendSimplePacket(GS_RINGTYPE_MEMWRITE8, mem&0x13ff, value, 0);
}
GIF_LOG("GS write 8 at %8.8lx with data %8.8lx\n", mem, value);
GIF_LOG("GS write 8 at %8.8lx with data %8.8lx", mem, value);
}
__forceinline void _gsSMODEwrite( u32 mem, u32 value )
@ -391,7 +391,7 @@ __forceinline void _gsSMODEwrite( u32 mem, u32 value )
__forceinline void gsWrite16(u32 mem, u16 value)
{
GIF_LOG("GS write 16 at %8.8lx with data %8.8lx\n", mem, value);
GIF_LOG("GS write 16 at %8.8lx with data %8.8lx", mem, value);
_gsSMODEwrite( mem, value );
@ -422,7 +422,7 @@ __forceinline void gsWrite16(u32 mem, u16 value)
__forceinline void gsWrite32(u32 mem, u32 value)
{
jASSUME( (mem & 3) == 0 );
GIF_LOG("GS write 32 at %8.8lx with data %8.8lx\n", mem, value);
GIF_LOG("GS write 32 at %8.8lx with data %8.8lx", mem, value);
_gsSMODEwrite( mem, value );
@ -471,7 +471,7 @@ void __fastcall gsWrite64_page_01( u32 mem, const mem64_t* value )
void __fastcall gsWrite64_generic( u32 mem, const mem64_t* value )
{
const u32* const srcval32 = (u32*)value;
GIF_LOG("GS Write64 at %8.8lx with data %8.8x_%8.8x\n", mem, srcval32[1], srcval32[0]);
GIF_LOG("GS Write64 at %8.8lx with data %8.8x_%8.8x", mem, srcval32[1], srcval32[0]);
*(u64*)PS2GS_BASE(mem) = *value;
@ -508,7 +508,7 @@ void __fastcall gsWrite128_generic( u32 mem, const mem128_t* value )
{
const u32* const srcval32 = (u32*)value;
GIF_LOG("GS Write128 at %8.8lx with data %8.8x_%8.8x_%8.8x_%8.8x \n", mem,
GIF_LOG("GS Write128 at %8.8lx with data %8.8x_%8.8x_%8.8x_%8.8x", mem,
srcval32[3], srcval32[2], srcval32[1], srcval32[0]);
const uint masked_mem = mem & 0x13ff;
@ -528,7 +528,7 @@ void __fastcall gsWrite128_generic( u32 mem, const mem128_t* value )
// This function is left in for now for debugging/reference purposes.
__forceinline void gsWrite64(u32 mem, u64 value)
{
GIF_LOG("GS write 64 at %8.8lx with data %8.8lx_%8.8lx\n", mem, ((u32*)&value)[1], (u32)value);
GIF_LOG("GS write 64 at %8.8lx with data %8.8lx_%8.8lx", mem, ((u32*)&value)[1], (u32)value);
switch (mem)
{
@ -559,26 +559,26 @@ __forceinline void gsWrite64(u32 mem, u64 value)
__forceinline u8 gsRead8(u32 mem)
{
GIF_LOG("GS read 8 from %8.8lx value: %8.8lx\n", mem, *(u8*)PS2GS_BASE(mem));
GIF_LOG("GS read 8 from %8.8lx value: %8.8lx", mem, *(u8*)PS2GS_BASE(mem));
return *(u8*)PS2GS_BASE(mem);
}
__forceinline u16 gsRead16(u32 mem)
{
GIF_LOG("GS read 16 from %8.8lx value: %8.8lx\n", mem, *(u16*)PS2GS_BASE(mem));
GIF_LOG("GS read 16 from %8.8lx value: %8.8lx", mem, *(u16*)PS2GS_BASE(mem));
return *(u16*)PS2GS_BASE(mem);
}
__forceinline u32 gsRead32(u32 mem)
{
GIF_LOG("GS read 32 from %8.8lx value: %8.8lx\n", mem, *(u32*)PS2GS_BASE(mem));
GIF_LOG("GS read 32 from %8.8lx value: %8.8lx", mem, *(u32*)PS2GS_BASE(mem));
return *(u32*)PS2GS_BASE(mem);
}
__forceinline u64 gsRead64(u32 mem)
{
// fixme - PS2GS_BASE(mem+4) = (g_RealGSMem+(mem + 4 & 0x13ff))
GIF_LOG("GS read 64 from %8.8lx value: %8.8lx_%8.8lx\n", mem, *(u32*)PS2GS_BASE(mem+4), *(u32*)PS2GS_BASE(mem) );
GIF_LOG("GS read 64 from %8.8lx value: %8.8lx_%8.8lx", mem, *(u32*)PS2GS_BASE(mem+4), *(u32*)PS2GS_BASE(mem) );
return *(u64*)PS2GS_BASE(mem);
}

22
pcsx2/Gif.cpp
View File

@ -36,7 +36,7 @@ static int gspath3done=0;
static int gscycles = 0;
__forceinline void gsInterrupt() {
GIF_LOG("gsInterrupt: %8.8x\n", cpuRegs.cycle);
GIF_LOG("gsInterrupt: %8.8x", cpuRegs.cycle);
if((gif->chcr & 0x100) == 0){
//Console::WriteLn("Eh? why are you still interrupting! chcr %x, qwc %x, done = %x", params gif->chcr, gif->qwc, done);
@ -161,7 +161,7 @@ void GIFdma()
return;
}
GIF_LOG("dmaGIFstart chcr = %lx, madr = %lx, qwc = %lx\n tadr = %lx, asr0 = %lx, asr1 = %lx\n", gif->chcr, gif->madr, gif->qwc, gif->tadr, gif->asr0, gif->asr1);
GIF_LOG("dmaGIFstart chcr = %lx, madr = %lx, qwc = %lx\n tadr = %lx, asr0 = %lx, asr1 = %lx", gif->chcr, gif->madr, gif->qwc, gif->tadr, gif->asr0, gif->asr1);
#ifndef GSPATH3FIX
if ( !(psHu32(GIF_MODE) & 0x4) ) {
@ -207,10 +207,10 @@ void GIFdma()
gif->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
gif->madr = ptag[1]; //MADR = ADDR field
gspath3done = hwDmacSrcChainWithStack(gif, id);
GIF_LOG("PTH3 MASK gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n", ptag[1], ptag[0], gif->qwc, id, gif->madr);
GIF_LOG("PTH3 MASK gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx", ptag[1], ptag[0], gif->qwc, id, gif->madr);
if ((gif->chcr & 0x80) && ptag[0] >> 31) { //Check TIE bit of CHCR and IRQ bit of tag
GIF_LOG("PATH3 MSK dmaIrq Set\n");
GIF_LOG("PATH3 MSK dmaIrq Set");
Console::WriteLn("GIF TIE");
gspath3done |= 1;
}
@ -285,7 +285,7 @@ void GIFdma()
gif->madr = ptag[1]; //MADR = ADDR field
gspath3done = hwDmacSrcChainWithStack(gif, id);
GIF_LOG("gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n", ptag[1], ptag[0], gif->qwc, id, gif->madr);
GIF_LOG("gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx", ptag[1], ptag[0], gif->qwc, id, gif->madr);
if ((psHu32(DMAC_CTRL) & 0xC0) == 0x80) { // STD == GIF
// there are still bugs, need to also check if gif->madr +16*qwc >= stadr, if not, stall
@ -305,7 +305,7 @@ void GIFdma()
FreezeRegs(0);
if ((gif->chcr & 0x80) && ptag[0] >> 31) { //Check TIE bit of CHCR and IRQ bit of tag
GIF_LOG("dmaIrq Set\n");
GIF_LOG("dmaIrq Set");
gspath3done = 1;
//gif->qwc = 0;
}
@ -500,7 +500,7 @@ void mfifoGIFtransfer(int qwc) {
if(!(gif->chcr & 0x100))return;
if(gifstate == GIF_STATE_STALL) return;
}
SPR_LOG("mfifoGIFtransfer %x madr %x, tadr %x\n", gif->chcr, gif->madr, gif->tadr);
SPR_LOG("mfifoGIFtransfer %x madr %x, tadr %x", gif->chcr, gif->madr, gif->tadr);
@ -523,7 +523,7 @@ void mfifoGIFtransfer(int qwc) {
mfifocycles += 2;
gif->chcr = ( gif->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 );
SPR_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx mfifo qwc = %x spr0 madr = %x\n",
SPR_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx mfifo qwc = %x spr0 madr = %x",
ptag[1], ptag[0], gif->qwc, id, gif->madr, gif->tadr, gifqwc, spr0->madr);
gifqwc--;
@ -559,14 +559,14 @@ void mfifoGIFtransfer(int qwc) {
break;
}
if ((gif->chcr & 0x80) && (ptag[0] >> 31)) {
SPR_LOG("dmaIrq Set\n");
SPR_LOG("dmaIrq Set");
gifstate = GIF_STATE_DONE;
gifmfifoirq = 1;
}
}
FreezeRegs(1);
if (mfifoGIFchain() == -1) {
Console::WriteLn("GIF dmaChain error size=%d, madr=%lx, tadr=%lx\n", params
Console::WriteLn("GIF dmaChain error size=%d, madr=%lx, tadr=%lx", params
gif->qwc, gif->madr, gif->tadr);
gifstate = GIF_STATE_STALL;
}
@ -575,7 +575,7 @@ void mfifoGIFtransfer(int qwc) {
if(gif->qwc == 0 && gifstate == GIF_STATE_DONE) gifstate = GIF_STATE_STALL;
CPU_INT(11,mfifocycles);
SPR_LOG("mfifoGIFtransfer end %x madr %x, tadr %x\n", gif->chcr, gif->madr, gif->tadr);
SPR_LOG("mfifoGIFtransfer end %x madr %x, tadr %x", gif->chcr, gif->madr, gif->tadr);
}
void gifMFIFOInterrupt()

104
pcsx2/Hw.cpp
View File

@ -81,7 +81,7 @@ __forceinline void intcInterrupt()
}
if ((psHu32(INTC_STAT) & psHu32(INTC_MASK)) == 0) return;
HW_LOG("intcInterrupt %x\n", psHu32(INTC_STAT) & psHu32(INTC_MASK));
HW_LOG("intcInterrupt %x", psHu32(INTC_STAT) & psHu32(INTC_MASK));
if(psHu32(INTC_STAT) & 0x2){
counters[0].hold = rcntRcount(0);
counters[1].hold = rcntRcount(1);
@ -99,7 +99,7 @@ __forceinline void dmacInterrupt()
if((psHu32(DMAC_CTRL) & 0x1) == 0) return;
HW_LOG("dmacInterrupt %x\n", (psHu16(0xe012) & psHu16(0xe010) ||
HW_LOG("dmacInterrupt %x", (psHu16(0xe012) & psHu16(0xe010) ||
psHu16(0xe010) & 0x8000));
cpuException(0x800, cpuRegs.branch);
@ -402,20 +402,20 @@ mem32_t __fastcall hwRead32(u32 mem)
case D2_SADR: regName = "DMA2_SADDR"; break;
}
HW_LOG( "Hardware Read32 at 0x%x (%s), value=0x%x\n", mem, regName, psHu32(mem) );
HW_LOG( "Hardware Read32 at 0x%x (%s), value=0x%x", mem, regName, psHu32(mem) );
}
break;
case 0x0b:
if( mem == D4_CHCR )
HW_LOG("Hardware Read32 at 0x%x (IPU1:DMA4_CHCR), value=0x%x\n", mem, psHu32(mem));
HW_LOG("Hardware Read32 at 0x%x (IPU1:DMA4_CHCR), value=0x%x", mem, psHu32(mem));
break;
case 0x0c:
case 0x0d:
case 0x0e:
if( mem == DMAC_STAT )
HW_LOG("DMAC_STAT Read32, value=0x%x\n", psHu32(DMAC_STAT));
HW_LOG("DMAC_STAT Read32, value=0x%x", psHu32(DMAC_STAT));
break;
jNO_DEFAULT;
@ -486,163 +486,163 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
return;
case 0x10008000: // dma0 - vif0
DMA_LOG("VIF0dma %lx\n", value);
DMA_LOG("VIF0dma %lx", value);
DmaExec(dmaVIF0, mem, value);
break;
//------------------------------------------------------------------
case 0x10009000: // dma1 - vif1 - chcr
DMA_LOG("VIF1dma CHCR %lx\n", value);
DMA_LOG("VIF1dma CHCR %lx", value);
DmaExec(dmaVIF1, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x10009010: // dma1 - vif1 - madr
HW_LOG("VIF1dma Madr %lx\n", value);
HW_LOG("VIF1dma Madr %lx", value);
psHu32(mem) = value;//dma1 madr
break;
case 0x10009020: // dma1 - vif1 - qwc
HW_LOG("VIF1dma QWC %lx\n", value);
HW_LOG("VIF1dma QWC %lx", value);
psHu32(mem) = value;//dma1 qwc
break;
case 0x10009030: // dma1 - vif1 - tadr
HW_LOG("VIF1dma TADR %lx\n", value);
HW_LOG("VIF1dma TADR %lx", value);
psHu32(mem) = value;//dma1 tadr
break;
case 0x10009040: // dma1 - vif1 - asr0
HW_LOG("VIF1dma ASR0 %lx\n", value);
HW_LOG("VIF1dma ASR0 %lx", value);
psHu32(mem) = value;//dma1 asr0
break;
case 0x10009050: // dma1 - vif1 - asr1
HW_LOG("VIF1dma ASR1 %lx\n", value);
HW_LOG("VIF1dma ASR1 %lx", value);
psHu32(mem) = value;//dma1 asr1
break;
case 0x10009080: // dma1 - vif1 - sadr
HW_LOG("VIF1dma SADR %lx\n", value);
HW_LOG("VIF1dma SADR %lx", value);
psHu32(mem) = value;//dma1 sadr
break;
#endif
//------------------------------------------------------------------
case 0x1000a000: // dma2 - gif
DMA_LOG("0x%8.8x hwWrite32: GSdma %lx\n", cpuRegs.cycle, value);
DMA_LOG("0x%8.8x hwWrite32: GSdma %lx", cpuRegs.cycle, value);
DmaExec(dmaGIF, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000a010:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000a020:
psHu32(mem) = value;//dma2 qwc
HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000a030:
psHu32(mem) = value;//dma2 taddr
HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x",mem,value);
break;
case 0x1000a040:
psHu32(mem) = value;//dma2 asr0
HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x",mem,value);
break;
case 0x1000a050:
psHu32(mem) = value;//dma2 asr1
HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x",mem,value);
break;
case 0x1000a080:
psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
//------------------------------------------------------------------
case 0x1000b000: // dma3 - fromIPU
DMA_LOG("IPU0dma %lx\n", value);
DMA_LOG("IPU0dma %lx", value);
DmaExec(dmaIPU0, mem, value);
break;
//------------------------------------------------------------------
#ifdef PCSX2_DEVBUILD
case 0x1000b010:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b020:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000b030:
psHu32(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b080:
psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
//------------------------------------------------------------------
case 0x1000b400: // dma4 - toIPU
DMA_LOG("IPU1dma %lx\n", value);
DMA_LOG("IPU1dma %lx", value);
DmaExec(dmaIPU1, mem, value);
break;
//------------------------------------------------------------------
#ifdef PCSX2_DEVBUILD
case 0x1000b410:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b420:
psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000b430:
psHu32(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b480:
psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
//------------------------------------------------------------------
case 0x1000c000: // dma5 - sif0
DMA_LOG("SIF0dma %lx\n", value);
DMA_LOG("SIF0dma %lx", value);
//if (value == 0) psxSu32(0x30) = 0x40000;
DmaExec(dmaSIF0, mem, value);
break;
//------------------------------------------------------------------
case 0x1000c400: // dma6 - sif1
DMA_LOG("SIF1dma %lx\n", value);
DMA_LOG("SIF1dma %lx", value);
DmaExec(dmaSIF1, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000c420: // dma6 - sif1 - qwc
HW_LOG("SIF1dma QWC = %lx\n", value);
HW_LOG("SIF1dma QWC = %lx", value);
psHu32(mem) = value;
break;
case 0x1000c430: // dma6 - sif1 - tadr
HW_LOG("SIF1dma TADR = %lx\n", value);
HW_LOG("SIF1dma TADR = %lx", value);
psHu32(mem) = value;
break;
#endif
//------------------------------------------------------------------
case 0x1000c800: // dma7 - sif2
DMA_LOG("SIF2dma %lx\n", value);
DMA_LOG("SIF2dma %lx", value);
DmaExec(dmaSIF2, mem, value);
break;
//------------------------------------------------------------------
case 0x1000d000: // dma8 - fromSPR
DMA_LOG("fromSPRdma %lx\n", value);
DMA_LOG("fromSPRdma %lx", value);
DmaExec(dmaSPR0, mem, value);
break;
//------------------------------------------------------------------
case 0x1000d400: // dma9 - toSPR
DMA_LOG("toSPRdma %lx\n", value);
DMA_LOG("toSPRdma %lx", value);
DmaExec(dmaSPR1, mem, value);
break;
//------------------------------------------------------------------
case 0x1000e000: // DMAC_CTRL
HW_LOG("DMAC_CTRL Write 32bit %x\n", value);
HW_LOG("DMAC_CTRL Write 32bit %x", value);
psHu32(0xe000) = value;
break;
case 0x1000e010: // DMAC_STAT
HW_LOG("DMAC_STAT Write 32bit %x\n", value);
HW_LOG("DMAC_STAT Write 32bit %x", value);
psHu16(0xe010)&= ~(value & 0xffff); // clear on 1
psHu16(0xe012) ^= (u16)(value >> 16);
@ -650,13 +650,13 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
break;
//------------------------------------------------------------------
case 0x1000f000: // INTC_STAT
HW_LOG("INTC_STAT Write 32bit %x\n", value);
HW_LOG("INTC_STAT Write 32bit %x", value);
psHu32(0xf000)&=~value;
//cpuTestINTCInts();
break;
case 0x1000f010: // INTC_MASK
HW_LOG("INTC_MASK Write 32bit %x\n", value);
HW_LOG("INTC_MASK Write 32bit %x", value);
psHu32(0xf010) ^= (u16)value;
cpuTestINTCInts();
break;
@ -672,7 +672,7 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
break;
//------------------------------------------------------------------
case 0x1000f590: // DMAC_ENABLEW
HW_LOG("DMAC_ENABLEW Write 32bit %lx\n", value);
HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
psHu32(0xf590) = value;
psHu32(0xf520) = value;
return;
@ -698,12 +698,12 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
//------------------------------------------------------------------
case 0x1000f130:
case 0x1000f410:
HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)\n", mem, value, cpuRegs.CP0.n.Status.val);
HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)", mem, value, cpuRegs.CP0.n.Status.val);
break;
//------------------------------------------------------------------
default:
psHu32(mem) = value;
HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)\n", mem, value, cpuRegs.CP0.n.Status.val);
HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)", mem, value, cpuRegs.CP0.n.Status.val);
break;
}
}
@ -745,7 +745,7 @@ __forceinline void hwWrite64(u32 mem, u64 value)
case GIF_MODE:
#ifdef GSPATH3FIX
Console::Status("GIFMODE64 %x\n", params value);
Console::Status("GIFMODE64 %x", params value);
#endif
psHu64(GIF_MODE) = value;
if (value & 0x1) psHu32(GIF_STAT)|= 0x1;
@ -758,17 +758,17 @@ __forceinline void hwWrite64(u32 mem, u64 value)
return;
case 0x1000a000: // dma2 - gif
DMA_LOG("0x%8.8x hwWrite64: GSdma %lx\n", cpuRegs.cycle, value);
DMA_LOG("0x%8.8x hwWrite64: GSdma %lx", cpuRegs.cycle, value);
DmaExec(dmaGIF, mem, value);
break;
case 0x1000e000: // DMAC_CTRL
HW_LOG("DMAC_CTRL Write 64bit %x\n", value);
HW_LOG("DMAC_CTRL Write 64bit %x", value);
psHu64(mem) = value;
break;
case 0x1000e010: // DMAC_STAT
HW_LOG("DMAC_STAT Write 64bit %x\n", value);
HW_LOG("DMAC_STAT Write 64bit %x", value);
val32 = (u32)value;
psHu16(0xe010)&= ~(val32 & 0xffff); // clear on 1
val32 = val32 >> 16;
@ -789,13 +789,13 @@ __forceinline void hwWrite64(u32 mem, u64 value)
break;
case 0x1000f000: // INTC_STAT
HW_LOG("INTC_STAT Write 64bit %x\n", value);
HW_LOG("INTC_STAT Write 64bit %x", value);
psHu32(INTC_STAT)&=~value;
cpuTestINTCInts();
break;
case 0x1000f010: // INTC_MASK
HW_LOG("INTC_MASK Write 32bit %x\n", value);
HW_LOG("INTC_MASK Write 32bit %x", value);
for (i=0; i<16; i++) { // reverse on 1
const int s = (1<<i);
if (value & s) {
@ -816,7 +816,7 @@ __forceinline void hwWrite64(u32 mem, u64 value)
default:
psHu64(mem) = value;
HW_LOG("Unknown Hardware write 64 at %x with value %x (status=%x)\n",mem,value, cpuRegs.CP0.n.Status.val);
HW_LOG("Unknown Hardware write 64 at %x with value %x (status=%x)",mem,value, cpuRegs.CP0.n.Status.val);
break;
}
}
@ -842,7 +842,7 @@ __forceinline void hwWrite128(u32 mem, const u64 *value)
psHu64(mem ) = value[0];
psHu64(mem+8) = value[1];
HW_LOG("Unknown Hardware write 128 at %x with value %x_%x (status=%x)\n", mem, value[1], value[0], cpuRegs.CP0.n.Status.val);
HW_LOG("Unknown Hardware write 128 at %x with value %x_%x (status=%x)", mem, value[1], value[0], cpuRegs.CP0.n.Status.val);
break;
}
}

2
pcsx2/Hw.h
View File

@ -347,7 +347,7 @@ static __forceinline u8* dmaGetAddr(u32 mem)
static __forceinline void *dmaGetAddr(u32 addr) {
u8 *ptr;
// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x\n", addr); }
// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
if (addr & 0x80000000) { // teh sux why the f00k 0xE0000000
return (void*)&psS[addr & 0x3ff0];

22
pcsx2/HwRead.cpp
View File

@ -106,7 +106,7 @@ __forceinline u8 hwRead8(u32 mem)
}
ret = psHu8(mem);
HW_LOG("Unknown Hardware Read 8 from 0x%x = 0x%x\n", mem, ret);
HW_LOG("Unknown Hardware Read 8 from 0x%x = 0x%x", mem, ret);
break;
}
@ -156,7 +156,7 @@ __forceinline u16 hwRead16(u32 mem)
return (u16)ret;
}
ret = psHu16(mem);
HW_LOG("Hardware Read16 at 0x%x, value= 0x%x\n", ret, mem);
HW_LOG("Hardware Read16 at 0x%x, value= 0x%x", ret, mem);
break;
}
return ret;
@ -217,11 +217,11 @@ static __forceinline mem32_t __hwRead32_page_0F( u32 mem, bool intchack )
case 0xf000:
if( intchack ) IntCHackCheck();
// This one is checked alot, so leave it commented out unless you love 600 meg logfiles.
//HW_LOG("INTC_STAT Read 32bit %x\n", psHu32(0xf010));
//HW_LOG("INTC_STAT Read 32bit %x", psHu32(0xf010));
break;
case 0xf010:
HW_LOG("INTC_MASK Read32, value=0x%x\n", psHu32(INTC_MASK));
HW_LOG("INTC_MASK Read32, value=0x%x", psHu32(INTC_MASK));
break;
case 0xf130: // 0x1000f130
@ -314,19 +314,19 @@ mem32_t __fastcall hwRead32_generic(u32 mem)
case D2_SADR: regName = "DMA2_SADDR"; break;
}
HW_LOG( "Hardware Read32 at 0x%x (%s), value=0x%x\n", mem, regName, psHu32(mem) );
HW_LOG( "Hardware Read32 at 0x%x (%s), value=0x%x", mem, regName, psHu32(mem) );
}
break;
case 0x0b:
if( mem == D4_CHCR )
HW_LOG("Hardware Read32 at 0x%x (IPU1:DMA4_CHCR), value=0x%x\n", mem, psHu32(mem));
HW_LOG("Hardware Read32 at 0x%x (IPU1:DMA4_CHCR), value=0x%x", mem, psHu32(mem));
break;
case 0x0c:
case 0x0e:
if( mem == DMAC_STAT)
HW_LOG("DMAC_STAT Read32, value=0x%x\n", psHu32(DMAC_STAT));
HW_LOG("DMAC_STAT Read32, value=0x%x", psHu32(DMAC_STAT));
break;
jNO_DEFAULT;
@ -358,13 +358,13 @@ void __fastcall hwRead64_generic_INTC_HACK(u32 mem, mem64_t* result )
if( mem == INTC_STAT ) IntCHackCheck();
*result = psHu64(mem);
HW_LOG("Unknown Hardware Read 64 at %x\n",mem);
HW_LOG("Unknown Hardware Read 64 at %x",mem);
}
void __fastcall hwRead64_generic(u32 mem, mem64_t* result )
{
*result = psHu64(mem);
HW_LOG("Unknown Hardware Read 64 at %x\n",mem);
HW_LOG("Unknown Hardware Read 64 at %x",mem);
}
/////////////////////////////////////////////////////////////////////////
@ -385,7 +385,7 @@ void __fastcall hwRead128_page_01(u32 mem, mem128_t* result )
void __fastcall hwRead128_page_02(u32 mem, mem128_t* result )
{
// IPU is currently unhandled in 128 bit mode.
HW_LOG("Unknown Hardware Read 128 at %x (IPU)\n",mem);
HW_LOG("Unknown Hardware Read 128 at %x (IPU)",mem);
}
void __fastcall hwRead128_generic(u32 mem, mem128_t* out)
@ -393,5 +393,5 @@ void __fastcall hwRead128_generic(u32 mem, mem128_t* out)
out[0] = psHu64(mem);
out[1] = psHu64(mem+8);
HW_LOG("Unknown Hardware Read 128 at %x\n",mem);
HW_LOG("Unknown Hardware Read 128 at %x",mem);
}

138
pcsx2/HwWrite.cpp
View File

@ -151,54 +151,54 @@ void hwWrite8(u32 mem, u8 value) {
// vif1Write32(mem & ~0x2, value << 16);
// break;
case 0x10008001: // dma0 - vif0
DMA_LOG("VIF0dma EXECUTE, value=0x%x\n", value);
DMA_LOG("VIF0dma EXECUTE, value=0x%x", value);
DmaExec8(dmaVIF0, mem, value);
break;
case 0x10009001: // dma1 - vif1
DMA_LOG("VIF1dma EXECUTE, value=0x%x\n", value);
DMA_LOG("VIF1dma EXECUTE, value=0x%x", value);
if(value & 0x1) vif1.done = 0; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
DmaExec8(dmaVIF1, mem, value);
break;
case 0x1000a001: // dma2 - gif
DMA_LOG("GSdma EXECUTE, value=0x%x\n", value);
DMA_LOG("GSdma EXECUTE, value=0x%x", value);
DmaExec8(dmaGIF, mem, value);
break;
case 0x1000b001: // dma3 - fromIPU
DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value);
DMA_LOG("IPU0dma EXECUTE, value=0x%x", value);
DmaExec8(dmaIPU0, mem, value);
break;
case 0x1000b401: // dma4 - toIPU
DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value);
DMA_LOG("IPU1dma EXECUTE, value=0x%x", value);
DmaExec8(dmaIPU1, mem, value);
break;
case 0x1000c001: // dma5 - sif0
DMA_LOG("SIF0dma EXECUTE, value=0x%x\n", value);
DMA_LOG("SIF0dma EXECUTE, value=0x%x", value);
// if (value == 0) psxSu32(0x30) = 0x40000;
DmaExec8(dmaSIF0, mem, value);
break;
case 0x1000c401: // dma6 - sif1
DMA_LOG("SIF1dma EXECUTE, value=0x%x\n", value);
DMA_LOG("SIF1dma EXECUTE, value=0x%x", value);
DmaExec8(dmaSIF1, mem, value);
break;
case 0x1000c801: // dma7 - sif2
DMA_LOG("SIF2dma EXECUTE, value=0x%x\n", value);
DMA_LOG("SIF2dma EXECUTE, value=0x%x", value);
DmaExec8(dmaSIF2, mem, value);
break;
case 0x1000d001: // dma8 - fromSPR
DMA_LOG("fromSPRdma8 EXECUTE, value=0x%x\n", value);
DMA_LOG("fromSPRdma8 EXECUTE, value=0x%x", value);
DmaExec8(dmaSPR0, mem, value);
break;
case 0x1000d401: // dma9 - toSPR
DMA_LOG("toSPRdma8 EXECUTE, value=0x%x\n", value);
DMA_LOG("toSPRdma8 EXECUTE, value=0x%x", value);
DmaExec8(dmaSPR1, mem, value);
break;
@ -227,7 +227,7 @@ void hwWrite8(u32 mem, u8 value) {
default:
psHu8(mem) = value;
}
HW_LOG("Unknown Hardware write 8 at %x with value %x\n", mem, value);
HW_LOG("Unknown Hardware write 8 at %x with value %x", mem, value);
break;
}
}
@ -258,125 +258,125 @@ __forceinline void hwWrite16(u32 mem, u16 value)
case 0x10001820: rcntWtarget(3, value); break;
case 0x10008000: // dma0 - vif0
DMA_LOG("VIF0dma %lx\n", value);
DMA_LOG("VIF0dma %lx", value);
DmaExec16(dmaVIF0, mem, value);
break;
case 0x10009000: // dma1 - vif1 - chcr
DMA_LOG("VIF1dma CHCR %lx\n", value);
DMA_LOG("VIF1dma CHCR %lx", value);
if(value & 0x100) vif1.done = 0; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
DmaExec16(dmaVIF1, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x10009010: // dma1 - vif1 - madr
HW_LOG("VIF1dma Madr %lx\n", value);
HW_LOG("VIF1dma Madr %lx", value);
psHu16(mem) = value;//dma1 madr
break;
case 0x10009020: // dma1 - vif1 - qwc
HW_LOG("VIF1dma QWC %lx\n", value);
HW_LOG("VIF1dma QWC %lx", value);
psHu16(mem) = value;//dma1 qwc
break;
case 0x10009030: // dma1 - vif1 - tadr
HW_LOG("VIF1dma TADR %lx\n", value);
HW_LOG("VIF1dma TADR %lx", value);
psHu16(mem) = value;//dma1 tadr
break;
case 0x10009040: // dma1 - vif1 - asr0
HW_LOG("VIF1dma ASR0 %lx\n", value);
HW_LOG("VIF1dma ASR0 %lx", value);
psHu16(mem) = value;//dma1 asr0
break;
case 0x10009050: // dma1 - vif1 - asr1
HW_LOG("VIF1dma ASR1 %lx\n", value);
HW_LOG("VIF1dma ASR1 %lx", value);
psHu16(mem) = value;//dma1 asr1
break;
case 0x10009080: // dma1 - vif1 - sadr
HW_LOG("VIF1dma SADR %lx\n", value);
HW_LOG("VIF1dma SADR %lx", value);
psHu16(mem) = value;//dma1 sadr
break;
#endif
// ---------------------------------------------------
case 0x1000a000: // dma2 - gif
DMA_LOG("0x%8.8x hwWrite32: GSdma %lx\n", cpuRegs.cycle, value);
DMA_LOG("0x%8.8x hwWrite32: GSdma %lx", cpuRegs.cycle, value);
DmaExec16(dmaGIF, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000a010:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000a020:
psHu16(mem) = value;//dma2 qwc
HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000a030:
psHu16(mem) = value;//dma2 taddr
HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x",mem,value);
break;
case 0x1000a040:
psHu16(mem) = value;//dma2 asr0
HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x",mem,value);
break;
case 0x1000a050:
psHu16(mem) = value;//dma2 asr1
HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x",mem,value);
break;
case 0x1000a080:
psHu16(mem) = value;//dma2 saddr
HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000b000: // dma3 - fromIPU
DMA_LOG("IPU0dma %lx\n", value);
DMA_LOG("IPU0dma %lx", value);
DmaExec16(dmaIPU0, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000b010:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b020:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000b030:
psHu16(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b080:
psHu16(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000b400: // dma4 - toIPU
DMA_LOG("IPU1dma %lx\n", value);
DMA_LOG("IPU1dma %lx", value);
DmaExec16(dmaIPU1, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000b410:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b420:
psHu16(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x",mem,value);
break;
case 0x1000b430:
psHu16(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x",mem,value);
break;
case 0x1000b480:
psHu16(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x\n",mem,value);
HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x",mem,value);
break;
#endif
case 0x1000c000: // dma5 - sif0
DMA_LOG("SIF0dma %lx\n", value);
DMA_LOG("SIF0dma %lx", value);
// if (value == 0) psxSu32(0x30) = 0x40000;
DmaExec16(dmaSIF0, mem, value);
break;
@ -385,36 +385,36 @@ __forceinline void hwWrite16(u32 mem, u16 value)
//?
break;
case 0x1000c400: // dma6 - sif1
DMA_LOG("SIF1dma %lx\n", value);
DMA_LOG("SIF1dma %lx", value);
DmaExec16(dmaSIF1, mem, value);
break;
#ifdef PCSX2_DEVBUILD
case 0x1000c420: // dma6 - sif1 - qwc
HW_LOG("SIF1dma QWC = %lx\n", value);
HW_LOG("SIF1dma QWC = %lx", value);
psHu16(mem) = value;
break;
case 0x1000c430: // dma6 - sif1 - tadr
HW_LOG("SIF1dma TADR = %lx\n", value);
HW_LOG("SIF1dma TADR = %lx", value);
psHu16(mem) = value;
break;
#endif
case 0x1000c800: // dma7 - sif2
DMA_LOG("SIF2dma %lx\n", value);
DMA_LOG("SIF2dma %lx", value);
DmaExec16(dmaSIF2, mem, value);
break;
case 0x1000c802:
//?
break;
case 0x1000d000: // dma8 - fromSPR
DMA_LOG("fromSPRdma %lx\n", value);
DMA_LOG("fromSPRdma %lx", value);
DmaExec16(dmaSPR0, mem, value);
break;
case 0x1000d400: // dma9 - toSPR
DMA_LOG("toSPRdma %lx\n", value);
DMA_LOG("toSPRdma %lx", value);
DmaExec16(dmaSPR1, mem, value);
break;
case 0x1000f592: // DMAC_ENABLEW
@ -451,7 +451,7 @@ __forceinline void hwWrite16(u32 mem, u16 value)
default:
psHu16(mem) = value;
HW_LOG("Unknown Hardware write 16 at %x with value %x\n",mem,value);
HW_LOG("Unknown Hardware write 16 at %x with value %x",mem,value);
}
}
@ -574,7 +574,7 @@ void __fastcall hwWrite32_page_0B( u32 mem, u32 value )
case D4_SADR: regName = "IPU1DMA_SADDR"; break;
}
HW_LOG( "Hardware Write32 at 0x%x (%s), value=0x%x\n", mem, regName, value );
HW_LOG( "Hardware Write32 at 0x%x (%s), value=0x%x", mem, regName, value );
psHu32(mem) = value;
}
@ -582,11 +582,11 @@ void __fastcall hwWrite32_page_0E( u32 mem, u32 value )
{
if( mem == DMAC_CTRL )
{
HW_LOG("DMAC_CTRL Write 32bit %x\n", value);
HW_LOG("DMAC_CTRL Write 32bit %x", value);
}
else if( mem == DMAC_STAT )
{
HW_LOG("DMAC_STAT Write 32bit %x\n", value);
HW_LOG("DMAC_STAT Write 32bit %x", value);
// lower 16 bits: clear on 1
// upper 16 bits: reverse on 1
@ -611,13 +611,13 @@ void __fastcall hwWrite32_page_0F( u32 mem, u32 value )
switch( HELPSWITCH(mem) )
{
case HELPSWITCH(INTC_STAT):
HW_LOG("INTC_STAT Write 32bit %x\n", value);
HW_LOG("INTC_STAT Write 32bit %x", value);
psHu32(INTC_STAT) &= ~value;
//cpuTestINTCInts();
break;
case HELPSWITCH(INTC_MASK):
HW_LOG("INTC_MASK Write 32bit %x\n", value);
HW_LOG("INTC_MASK Write 32bit %x", value);
psHu32(INTC_MASK) ^= (u16)value;
cpuTestINTCInts();
break;
@ -653,7 +653,7 @@ void __fastcall hwWrite32_page_0F( u32 mem, u32 value )
break;
case HELPSWITCH(0x1000f590): // DMAC_ENABLEW
HW_LOG("DMAC_ENABLEW Write 32bit %lx\n", value);
HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
psHu32(0xf590) = value;
psHu32(0xf520) = value;
break;
@ -661,7 +661,7 @@ void __fastcall hwWrite32_page_0F( u32 mem, u32 value )
//------------------------------------------------------------------
case HELPSWITCH(0x1000f130):
case HELPSWITCH(0x1000f410):
HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)\n", mem, value, cpuRegs.CP0.n.Status.val);
HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)", mem, value, cpuRegs.CP0.n.Status.val);
break;
default:
@ -677,13 +677,13 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value )
switch (mem)
{
case D0_CHCR: // dma0 - vif0
DMA_LOG("VIF0dma EXECUTE, value=0x%x\n", value);
DMA_LOG("VIF0dma EXECUTE, value=0x%x", value);
DmaExec(dmaVIF0, mem, value);
return;
//------------------------------------------------------------------
case D1_CHCR: // dma1 - vif1 - chcr
DMA_LOG("VIF1dma EXECUTE, value=0x%x\n", value);
DMA_LOG("VIF1dma EXECUTE, value=0x%x", value);
if(value & 0x100)
{
vif1.done = 0; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO
@ -713,13 +713,13 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value )
//------------------------------------------------------------------
case 0x1000c000: // dma5 - sif0
DMA_LOG("SIF0dma EXECUTE, value=0x%x\n", value);
DMA_LOG("SIF0dma EXECUTE, value=0x%x", value);
//if (value == 0) psxSu32(0x30) = 0x40000;
DmaExec(dmaSIF0, mem, value);
return;
//------------------------------------------------------------------
case 0x1000c400: // dma6 - sif1
DMA_LOG("SIF1dma EXECUTE, value=0x%x\n", value);
DMA_LOG("SIF1dma EXECUTE, value=0x%x", value);
DmaExec(dmaSIF1, mem, value);
return;
@ -728,21 +728,21 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value )
//------------------------------------------------------------------
case 0x1000c800: // dma7 - sif2
DMA_LOG("SIF2dma EXECUTE, value=0x%x\n", value);
DMA_LOG("SIF2dma EXECUTE, value=0x%x", value);
DmaExec(dmaSIF2, mem, value);
return;
//------------------------------------------------------------------
case 0x1000d000: // dma8 - fromSPR
DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x\n", value);
DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value);
DmaExec(dmaSPR0, mem, value);
return;
//------------------------------------------------------------------
case 0x1000d400: // dma9 - toSPR
DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x\n", value);
DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value);
DmaExec(dmaSPR1, mem, value);
return;
}
HW_LOG( "Hardware Write32 at 0x%x (%s), value=0x%x\n", mem, regName, value );
HW_LOG( "Hardware Write32 at 0x%x (%s), value=0x%x", mem, regName, value );
psHu32(mem) = value;
}
@ -789,7 +789,7 @@ void __fastcall hwWrite64_page_03( u32 mem, const mem64_t* srcval )
case GIF_MODE:
{
#ifdef GSPATH3FIX
Console::Status("GIFMODE64 %x\n", params value);
Console::Status("GIFMODE64 %x", params value);
#endif
psHu64(GIF_MODE) = value;
@ -812,11 +812,11 @@ void __fastcall hwWrite64_page_0E( u32 mem, const mem64_t* srcval )
if( mem == DMAC_CTRL )
{
HW_LOG("DMAC_CTRL Write 64bit %x\n", value);
HW_LOG("DMAC_CTRL Write 64bit %x", value);
}
else if( mem == DMAC_STAT )
{
HW_LOG("DMAC_STAT Write 64bit %x\n", value);
HW_LOG("DMAC_STAT Write 64bit %x", value);
// lower 16 bits: clear on 1
// upper 16 bits: reverse on 1
@ -840,18 +840,18 @@ void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval )
switch (mem)
{
case 0x1000a000: // dma2 - gif
DMA_LOG("0x%8.8x hwWrite64: GSdma %x\n", cpuRegs.cycle, value);
DMA_LOG("0x%8.8x hwWrite64: GSdma %x", cpuRegs.cycle, value);
DmaExec(dmaGIF, mem, value);
break;
case INTC_STAT:
HW_LOG("INTC_STAT Write 64bit %x\n", (u32)value);
HW_LOG("INTC_STAT Write 64bit %x", (u32)value);
psHu32(INTC_STAT) &= ~value;
//cpuTestINTCInts();
break;
case INTC_MASK:
HW_LOG("INTC_MASK Write 64bit %x\n", (u32)value);
HW_LOG("INTC_MASK Write 64bit %x", (u32)value);
psHu32(INTC_MASK) ^= (u16)value;
cpuTestINTCInts();
break;
@ -868,7 +868,7 @@ void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval )
default:
psHu64(mem) = value;
HW_LOG("Unknown Hardware write 64 at %x with value %x (status=%x)\n",mem,value, cpuRegs.CP0.n.Status.val);
HW_LOG("Unknown Hardware write 64 at %x with value %x (status=%x)",mem,value, cpuRegs.CP0.n.Status.val);
break;
}
}
@ -883,13 +883,13 @@ void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval)
switch (mem)
{
case INTC_STAT:
HW_LOG("INTC_STAT Write 64bit %x\n", (u32)srcval[0]);
HW_LOG("INTC_STAT Write 64bit %x", (u32)srcval[0]);
psHu32(INTC_STAT) &= ~srcval[0];
//cpuTestINTCInts();
break;
case INTC_MASK:
HW_LOG("INTC_MASK Write 64bit %x\n", (u32)srcval[0]);
HW_LOG("INTC_MASK Write 64bit %x", (u32)srcval[0]);
psHu32(INTC_MASK) ^= (u16)srcval[0];
cpuTestINTCInts();
break;
@ -908,7 +908,7 @@ void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval)
psHu64(mem ) = srcval[0];
psHu64(mem+8) = srcval[1];
HW_LOG("Unknown Hardware write 128 at %x with value %x_%x (status=%x)\n", mem, srcval[1], srcval[0], cpuRegs.CP0.n.Status.val);
HW_LOG("Unknown Hardware write 128 at %x with value %x_%x (status=%x)", mem, srcval[1], srcval[0], cpuRegs.CP0.n.Status.val);
break;
}
}

76
pcsx2/IPU/IPU.cpp
View File

@ -248,7 +248,7 @@ __forceinline u32 ipuRead32(u32 mem)
ipuRegs->ctrl.CBP = coded_block_pattern;
if( !ipuRegs->ctrl.BUSY )
IPU_LOG("Ipu read32: IPU_CTRL=0x%08X %x\n", ipuRegs->ctrl._u32, cpuRegs.pc);
IPU_LOG("Ipu read32: IPU_CTRL=0x%08X %x", ipuRegs->ctrl._u32, cpuRegs.pc);
return ipuRegs->ctrl._u32;
@ -258,7 +258,7 @@ __forceinline u32 ipuRead32(u32 mem)
ipuRegs->ipubp |= g_BP.IFC<<8;
ipuRegs->ipubp |= (g_BP.FP+g_BP.bufferhasnew) << 16;
IPU_LOG("Ipu read32: IPU_BP=0x%08X\n", *(u32*)&g_BP);
IPU_LOG("Ipu read32: IPU_BP=0x%08X", *(u32*)&g_BP);
return ipuRegs->ipubp;
}
@ -281,7 +281,7 @@ __forceinline u64 ipuRead64(u32 mem)
//if(!ipuRegs->cmd.BUSY){
if( ipuRegs->cmd.DATA&0xffffff )
IPU_LOG("Ipu read64: IPU_CMD=BUSY=%x, DATA=%08X\n", ipuRegs->cmd.BUSY?1:0,ipuRegs->cmd.DATA);
IPU_LOG("Ipu read64: IPU_CMD=BUSY=%x, DATA=%08X", ipuRegs->cmd.BUSY?1:0,ipuRegs->cmd.DATA);
//return *(u64*)&ipuRegs->cmd;
break;
@ -294,13 +294,13 @@ __forceinline u64 ipuRead64(u32 mem)
break;
case 0x30: // IPU_TOP
IPU_LOG("Ipu read64: IPU_TOP=%x, bp = %d\n",ipuRegs->top,g_BP.BP);
IPU_LOG("Ipu read64: IPU_TOP=%x, bp = %d",ipuRegs->top,g_BP.BP);
//return *(u64*)&ipuRegs->top;
break;
default:
IPU_LOG("Ipu read64: Unknown=%x\n", mem);
IPU_LOG("Ipu read64: Unknown=%x", mem);
break;
}
return *(u64*)(((u8*)ipuRegs)+mem);
@ -351,7 +351,7 @@ __forceinline void ipuWrite32(u32 mem, u32 value)
switch (mem){
case 0x00: // IPU_CMD
IPU_LOG("Ipu write32: IPU_CMD=0x%08X\n",value);
IPU_LOG("Ipu write32: IPU_CMD=0x%08X",value);
IPUCMD_WRITE(value);
break;
@ -365,11 +365,11 @@ __forceinline void ipuWrite32(u32 mem, u32 value)
ipuSoftReset();
}
IPU_LOG("Ipu write32: IPU_CTRL=0x%08X\n",value);
IPU_LOG("Ipu write32: IPU_CTRL=0x%08X",value);
break;
default:
IPU_LOG("Ipu write32: Unknown=%x\n", mem);
IPU_LOG("Ipu write32: Unknown=%x", mem);
*(u32*)((u8*)ipuRegs + mem) = value;
break;
}
@ -388,12 +388,12 @@ __forceinline void ipuWrite64(u32 mem, u64 value)
switch( mem )
{
case 0x10:
IPU_LOG("Ipu write64: IPU_CMD=0x%08X\n",value);
IPU_LOG("Ipu write64: IPU_CMD=0x%08X",value);
IPUCMD_WRITE((u32)value);
break;
default:
IPU_LOG("Ipu write64: Unknown=%x\n", mem);
IPU_LOG("Ipu write64: Unknown=%x", mem);
*(u64*)((u8*)ipuRegs + mem) = value;
break;
}
@ -412,7 +412,7 @@ static void ipuBCLR(u32 val) {
ipuRegs->ctrl.BUSY = 0;
ipuRegs->cmd.BUSY = 0;
memzero_ptr<80>(readbits);
IPU_LOG("Clear IPU input FIFO. Set Bit offset=0x%X\n", g_BP.BP);
IPU_LOG("Clear IPU input FIFO. Set Bit offset=0x%X", g_BP.BP);
}
static __forceinline BOOL ipuIDEC(u32 val)
@ -420,7 +420,7 @@ static __forceinline BOOL ipuIDEC(u32 val)
tIPU_CMD_IDEC idec( val );
IPU_LOG("IPU IDEC command.\n");
IPU_LOG("IPU IDEC command.");
if (idec.FB){ IPU_LOG(" Skip %d bits.",idec.FB);}
IPU_LOG(" Quantizer step code=0x%X.",idec.QSC);
if (idec.DTD==0){ IPU_LOG(" Does not decode DT.");
@ -430,7 +430,7 @@ static __forceinline BOOL ipuIDEC(u32 val)
if (idec.DTE==1){ IPU_LOG(" Dither Enabled.");}
if (idec.OFM==0){ IPU_LOG(" Output format is RGB32.");
}else{ IPU_LOG(" Output format is RGB16.");}
IPU_LOG("\n");
IPU_LOG("");
g_BP.BP+= idec.FB;//skip FB bits
//from IPU_CTRL
@ -469,7 +469,7 @@ static __forceinline BOOL ipuBDEC(u32 val)
{
tIPU_CMD_BDEC bdec( val );
IPU_LOG("IPU BDEC(macroblock decode) command %x, num: 0x%x\n",cpuRegs.pc, s_bdec);
IPU_LOG("IPU BDEC(macroblock decode) command %x, num: 0x%x",cpuRegs.pc, s_bdec);
if (bdec.FB){ IPU_LOG(" Skip 0x%X bits.", bdec.FB);}
if (bdec.MBI){ IPU_LOG(" Intra MB.");}
else{ IPU_LOG(" Non-intra MB.");}
@ -477,7 +477,7 @@ static __forceinline BOOL ipuBDEC(u32 val)
else{ IPU_LOG(" Doesn't reset DC prediction value.");}
if (bdec.DT){ IPU_LOG(" Use field DCT.");}
else{ IPU_LOG(" Use frame DCT.");}
IPU_LOG(" Quantizer step=0x%X\n",bdec.QSC);
IPU_LOG(" Quantizer step=0x%X",bdec.QSC);
#ifdef _DEBUG
s_bdec++;
#endif
@ -555,7 +555,7 @@ static BOOL __fastcall ipuVDEC(u32 val) {
BigEndian(ipuRegs->top, ipuRegs->top);
IPU_LOG("IPU VDEC command data 0x%x(0x%x). Skip 0x%X bits/Table=%d (%s), pct %d\n",
IPU_LOG("IPU VDEC command data 0x%x(0x%x). Skip 0x%X bits/Table=%d (%s), pct %d",
ipuRegs->cmd.DATA,ipuRegs->cmd.DATA >> 16,val & 0x3f, (val >> 26) & 3, (val >> 26) & 1 ?
((val >> 26) & 2 ? "DMV" : "MBT") : (((val >> 26) & 2 ? "MC" : "MBAI")),ipuRegs->ctrl.PCT);
@ -575,7 +575,7 @@ static BOOL ipuFDEC(u32 val)
BigEndian(ipuRegs->cmd.DATA, ipuRegs->cmd.DATA);
ipuRegs->top = ipuRegs->cmd.DATA;
IPU_LOG("FDEC read: 0x%8.8x\n", ipuRegs->top);
IPU_LOG("FDEC read: 0x%8.8x", ipuRegs->top);
return TRUE;
}
@ -587,17 +587,17 @@ static __forceinline BOOL ipuSETIQ(u32 val)
if ((val >> 27) & 1){
g_nCmdPos[0] += getBits((u8*)niq + g_nCmdPos[0], 512-8*g_nCmdPos[0], 1); // 8*8*8
IPU_LOG("Read non-intra quantization matrix from IPU FIFO.\n");
IPU_LOG("Read non-intra quantization matrix from IPU FIFO.");
for (i=0; i<8; i++){
IPU_LOG("%02X %02X %02X %02X %02X %02X %02X %02X\n",
IPU_LOG("%02X %02X %02X %02X %02X %02X %02X %02X",
niq[i*8+0], niq[i*8+1], niq[i*8+2], niq[i*8+3],
niq[i*8+4], niq[i*8+5], niq[i*8+6], niq[i*8+7]);
}
}else{
g_nCmdPos[0] += getBits((u8*)iq+8*g_nCmdPos[0], 512-8*g_nCmdPos[0], 1);
IPU_LOG("Read intra quantization matrix from IPU FIFO.\n");
IPU_LOG("Read intra quantization matrix from IPU FIFO.");
for (i=0; i<8; i++){
IPU_LOG("%02X %02X %02X %02X %02X %02X %02X %02X\n",
IPU_LOG("%02X %02X %02X %02X %02X %02X %02X %02X",
iq[i*8+0], iq[i*8+1], iq[i*8+2], iq[i*8+3],
iq[i*8+4], iq[i*8+5], iq[i*8+6], iq[i*8+7]);
}
@ -612,12 +612,12 @@ static __forceinline BOOL ipuSETVQ(u32 val)
if( g_nCmdPos[0] == 32 )
{
IPU_LOG("IPU SETVQ command.\nRead VQCLUT table from IPU FIFO.\n");
IPU_LOG("IPU SETVQ command.\nRead VQCLUT table from IPU FIFO.");
IPU_LOG(
"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d "
"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d\n"
"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d"
"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d "
"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d\n",
"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d",
vqclut[0] >> 10, (vqclut[0] >> 5) & 0x1F, vqclut[0] & 0x1F,
vqclut[1] >> 10, (vqclut[1] >> 5) & 0x1F, vqclut[1] & 0x1F,
vqclut[2] >> 10, (vqclut[2] >> 5) & 0x1F, vqclut[2] & 0x1F,
@ -644,7 +644,7 @@ static BOOL __fastcall ipuCSC(u32 val)
{
tIPU_CMD_CSC csc( val );
IPU_LOG("IPU CSC(Colorspace conversion from YCbCr) command (%d).\n",csc.MBC);
IPU_LOG("IPU CSC(Colorspace conversion from YCbCr) command (%d).",csc.MBC);
if (csc.OFM)
IPU_LOG("Output format is RGB16. ");
else
@ -698,11 +698,11 @@ static BOOL ipuPACK(u32 val)
{
tIPU_CMD_CSC csc( val );
IPU_LOG("IPU PACK (Colorspace conversion from RGB32) command.\n");
IPU_LOG("IPU PACK (Colorspace conversion from RGB32) command.");
if (csc.OFM){ IPU_LOG("Output format is RGB16. ");}
else{ IPU_LOG("Output format is INDX4. ");}
if (csc.DTE){ IPU_LOG("Dithering enabled."); }
IPU_LOG("Number of macroblocks to be converted: %d\n", csc.MBC);
IPU_LOG("Number of macroblocks to be converted: %d", csc.MBC);
for (;g_nCmdIndex<(int)csc.MBC; g_nCmdIndex++){
@ -742,7 +742,7 @@ static BOOL ipuPACK(u32 val)
static void ipuSETTH(u32 val) {
s_thresh[0] = (val & 0xff);
s_thresh[1] = ((val>>16) & 0xff);
IPU_LOG("IPU SETTH (Set threshold value)command %x.\n", val&0xff00ff);
IPU_LOG("IPU SETTH (Set threshold value)command %x.", val&0xff00ff);
}
///////////////////////
@ -786,7 +786,7 @@ void IPUCMD_WRITE(u32 val) {
break;
case SCE_IPU_FDEC:
IPU_LOG("IPU FDEC command. Skip 0x%X bits, FIFO 0x%X qwords, BP 0x%X, FP %d, CHCR 0x%x, %x\n",
IPU_LOG("IPU FDEC command. Skip 0x%X bits, FIFO 0x%X qwords, BP 0x%X, FP %d, CHCR 0x%x, %x",
val & 0x3f,g_BP.IFC,(int)g_BP.BP,g_BP.FP,((DMACh*)&PS2MEM_HW[0xb400])->chcr,cpuRegs.pc);
g_BP.BP+= val & 0x3F;
@ -806,10 +806,10 @@ void IPUCMD_WRITE(u32 val) {
return;
case SCE_IPU_SETIQ:
IPU_LOG("IPU SETIQ command.\n");
IPU_LOG("IPU SETIQ command.");
if (val & 0x3f)
IPU_LOG("Skip %d bits.\n", val & 0x3f);
IPU_LOG("Skip %d bits.", val & 0x3f);
g_BP.BP+= val & 0x3F;
@ -1466,7 +1466,7 @@ int IPU1dma()
}
ipu1dma->chcr = (ipu1dma->chcr & 0xFFFF) | ( (*ptag) & 0xFFFF0000 );
IPU_LOG("IPU dmaIrq Set\n");
IPU_LOG("IPU dmaIrq Set");
IPU_INT_TO(totalqwc*BIAS);
g_nDMATransfer |= IPU_DMA_TIE1;
return totalqwc;
@ -1495,7 +1495,7 @@ int IPU1dma()
// Transfer Dn_QWC from Dn_MADR to GIF
if ((ipu1dma->chcr & 0xc) == 0 || ipu1dma->qwc > 0) { // Normal Mode
IPU_LOG("dmaIPU1 Normal size=%d, addr=%lx, fifosize=%x\n",
IPU_LOG("dmaIPU1 Normal size=%d, addr=%lx, fifosize=%x",
ipu1dma->qwc, ipu1dma->madr, 8 - g_BP.IFC);
IPU1chain();
IPU_INT_TO((ipu1cycles+totalqwc)*BIAS);
@ -1549,11 +1549,11 @@ int IPU1dma()
break;
default:
Console::Error("IPU ERROR: different transfer mode!, Please report to PCSX2 Team\n");
Console::Error("IPU ERROR: different transfer mode!, Please report to PCSX2 Team");
break;
}
IPU_LOG("dmaIPU1 dmaChain %8.8x_%8.8x size=%d, addr=%lx, fifosize=%x\n",
IPU_LOG("dmaIPU1 dmaChain %8.8x_%8.8x size=%d, addr=%lx, fifosize=%x",
ptag[1], ptag[0], ipu1dma->qwc, ipu1dma->madr, 8 - g_BP.IFC);
if( (ipu1dma->chcr & 0x80) && ptag[0] & 0x80000000 )
@ -1685,7 +1685,7 @@ int IPU0dma()
assert( !(ipu0dma->chcr&0x40) );
IPU_LOG("dmaIPU0 chcr = %lx, madr = %lx, qwc = %lx\n",
IPU_LOG("dmaIPU0 chcr = %lx, madr = %lx, qwc = %lx",
ipu0dma->chcr, ipu0dma->madr, ipu0dma->qwc);
assert((ipu0dma->chcr & 0xC) == 0 );
@ -1729,7 +1729,7 @@ void dmaIPU1() // toIPU
extern void GIFdma();
void ipu0Interrupt() {
IPU_LOG("ipu0Interrupt: %x\n", cpuRegs.cycle);
IPU_LOG("ipu0Interrupt: %x", cpuRegs.cycle);
if( g_nDMATransfer & IPU_DMA_FIREINT0 ) {
hwIntcIrq(INTC_IPU);
@ -1758,7 +1758,7 @@ void ipu0Interrupt() {
}
IPU_FORCEINLINE void ipu1Interrupt() {
IPU_LOG("ipu1Interrupt %x:\n", cpuRegs.cycle);
IPU_LOG("ipu1Interrupt %x:", cpuRegs.cycle);
if( g_nDMATransfer & IPU_DMA_FIREINT1 ) {
hwIntcIrq(INTC_IPU);

2
pcsx2/Interpreter.cpp
View File

@ -60,7 +60,7 @@ static void execI()
// Another method of instruction dumping:
/*if( cpuRegs.cycle > 0x4f24d714 )
{
//CPU_LOG( "%s\n", disR5900Current.getCString());
//CPU_LOG( "%s", disR5900Current.getCString());
disOut.clear();
opcode.disasm( disOut );
disOut += '\n';

2
pcsx2/IopBios.cpp
View File

@ -182,7 +182,7 @@ void bios_write() { // 0x35/0x03
}
pc0 = ra; return;
}
PSXBIOS_LOG("bios_%s: %x,%x,%x\n", biosB0n[0x35], a0, a1, a2);
PSXBIOS_LOG("bios_%s: %x,%x,%x", biosB0n[0x35], a0, a1, a2);
v0 = -1;
pc0 = ra;

38
pcsx2/IopCounters.cpp
View File

@ -154,7 +154,7 @@ static void __fastcall _rcntTestTarget( int i )
{
if( psxCounters[i].count < psxCounters[i].target ) return;
PSXCNT_LOG("IOP Counter[%d] target 0x%I64x >= 0x%I64x (mode: %x)\n",
PSXCNT_LOG("IOP Counter[%d] target 0x%I64x >= 0x%I64x (mode: %x)",
i, psxCounters[i].count, psxCounters[i].target, psxCounters[i].mode);
if (psxCounters[i].mode & IOPCNT_INT_TARGET)
@ -186,7 +186,7 @@ static __forceinline void _rcntTestOverflow( int i )
u64 maxTarget = ( i < 3 ) ? 0xffff : 0xfffffffful;
if( psxCounters[i].count <= maxTarget ) return;
PSXCNT_LOG("IOP Counter[%d] overflow 0x%I64x >= 0x%I64x (mode: %x)\n",
PSXCNT_LOG("IOP Counter[%d] overflow 0x%I64x >= 0x%I64x (mode: %x)",
i, psxCounters[i].count, maxTarget, psxCounters[i].mode );
if(psxCounters[i].mode & IOPCNT_INT_OVERFLOW)
@ -461,7 +461,7 @@ void psxRcntWcount16(int index, u32 value)
u32 change;
assert( index < 3 );
PSXCNT_LOG("IOP Counter[%d] writeCount16 = %x\n", index, value);
PSXCNT_LOG("IOP Counter[%d] writeCount16 = %x", index, value);
if(psxCounters[index].rate != PSXHBLANK)
{
@ -482,7 +482,7 @@ void psxRcntWcount32(int index, u32 value)
u32 change;
assert( index >= 3 && index < 6 );
PSXCNT_LOG("IOP Counter[%d] writeCount32 = %x\n", index, value);
PSXCNT_LOG("IOP Counter[%d] writeCount32 = %x", index, value);
if(psxCounters[index].rate != PSXHBLANK)
{
@ -500,7 +500,7 @@ void psxRcntWcount32(int index, u32 value)
void psxRcnt0Wmode(u32 value)
{
PSXCNT_LOG("IOP Counter[0] writeMode = %lx\n", value);
PSXCNT_LOG("IOP Counter[0] writeMode = %lx", value);
psxCounters[0].mode = value;
psxCounters[0].mode|= 0x0400;
@ -512,7 +512,7 @@ void psxRcnt0Wmode(u32 value)
if(psxCounters[0].mode & IOPCNT_ENABLE_GATE)
{
// gated counters are added up as per the h/vblank timers.
PSXCNT_LOG("IOP Counter[0] Gate Check set, value = %x\n", value);
PSXCNT_LOG("IOP Counter[0] Gate Check set, value = %x", value);
psxhblankgate |= 1;
}
else psxhblankgate &= ~1;
@ -526,7 +526,7 @@ void psxRcnt0Wmode(u32 value)
void psxRcnt1Wmode(u32 value)
{
PSXCNT_LOG("IOP Counter[0] writeMode = %lx\n", value);
PSXCNT_LOG("IOP Counter[0] writeMode = %lx", value);
psxCounters[1].mode = value;
psxCounters[1].mode|= 0x0400;
@ -537,7 +537,7 @@ void psxRcnt1Wmode(u32 value)
if(psxCounters[1].mode & IOPCNT_ENABLE_GATE)
{
PSXCNT_LOG("IOP Counter[1] Gate Check set, value = %x\n", value);
PSXCNT_LOG("IOP Counter[1] Gate Check set, value = %x", value);
psxvblankgate |= 1<<1;
}
else psxvblankgate &= ~(1<<1);
@ -550,7 +550,7 @@ void psxRcnt1Wmode(u32 value)
void psxRcnt2Wmode(u32 value)
{
PSXCNT_LOG("IOP Counter[0] writeMode = %lx\n", value);
PSXCNT_LOG("IOP Counter[0] writeMode = %lx", value);
psxCounters[2].mode = value;
psxCounters[2].mode|= 0x0400;
@ -575,7 +575,7 @@ void psxRcnt2Wmode(u32 value)
void psxRcnt3Wmode(u32 value)
{
PSXCNT_LOG("IOP Counter[3] writeMode = %lx\n", value);
PSXCNT_LOG("IOP Counter[3] writeMode = %lx", value);
psxCounters[3].mode = value;
psxCounters[3].rate = 1;
@ -586,7 +586,7 @@ void psxRcnt3Wmode(u32 value)
if(psxCounters[3].mode & IOPCNT_ENABLE_GATE)
{
PSXCNT_LOG("IOP Counter[3] Gate Check set, value = %x\n", value);
PSXCNT_LOG("IOP Counter[3] Gate Check set, value = %x", value);
psxvblankgate |= 1<<3;
}
else psxvblankgate &= ~(1<<3);
@ -599,7 +599,7 @@ void psxRcnt3Wmode(u32 value)
void psxRcnt4Wmode(u32 value)
{
PSXCNT_LOG("IOP Counter[4] writeMode = %lx\n", value);
PSXCNT_LOG("IOP Counter[4] writeMode = %lx", value);
psxCounters[4].mode = value;
psxCounters[4].mode|= 0x0400;
@ -626,7 +626,7 @@ void psxRcnt4Wmode(u32 value)
void psxRcnt5Wmode(u32 value)
{
PSXCNT_LOG("IOP Counter[5] writeMode = %lx\n", value);
PSXCNT_LOG("IOP Counter[5] writeMode = %lx", value);
psxCounters[5].mode = value;
psxCounters[5].mode|= 0x0400;
@ -654,7 +654,7 @@ void psxRcnt5Wmode(u32 value)
void psxRcntWtarget16(int index, u32 value)
{
assert( index < 3 );
PSXCNT_LOG("IOP Counter[%d] writeTarget16 = %lx\n", index, value);
PSXCNT_LOG("IOP Counter[%d] writeTarget16 = %lx", index, value);
psxCounters[index].target = value & 0xffff;
// protect the target from an early arrival.
@ -670,7 +670,7 @@ void psxRcntWtarget16(int index, u32 value)
void psxRcntWtarget32(int index, u32 value)
{
assert( index >= 3 && index < 6);
PSXCNT_LOG("IOP Counter[%d] writeTarget32 = %lx\n", index, value);
PSXCNT_LOG("IOP Counter[%d] writeTarget32 = %lx", index, value);
psxCounters[index].target = value;
@ -690,7 +690,7 @@ u16 psxRcntRcount16(int index)
assert( index < 3 );
PSXCNT_LOG("IOP Counter[%d] readCount16 = %lx\n", index, (u16)retval );
PSXCNT_LOG("IOP Counter[%d] readCount16 = %lx", index, (u16)retval );
// Don't count HBLANK timers
// Don't count stopped gates either.
@ -700,7 +700,7 @@ u16 psxRcntRcount16(int index)
{
u32 delta = (u32)((psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
retval += delta;
PSXCNT_LOG(" (delta = %lx)\n", delta );
PSXCNT_LOG(" (delta = %lx)", delta );
}
return (u16)retval;
@ -712,14 +712,14 @@ u32 psxRcntRcount32(int index)
assert( index >= 3 && index < 6 );
PSXCNT_LOG("IOP Counter[%d] readCount32 = %lx\n", index, retval );
PSXCNT_LOG("IOP Counter[%d] readCount32 = %lx", index, retval );
if( !( psxCounters[index].mode & IOPCNT_STOPPED ) &&
( psxCounters[index].rate != PSXHBLANK ) )
{
u32 delta = (u32)((psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
retval += delta;
PSXCNT_LOG(" (delta = %lx)\n", delta );
PSXCNT_LOG(" (delta = %lx)", delta );
}
return retval;

20
pcsx2/IopDma.cpp
View File

@ -58,18 +58,18 @@ static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _
switch (chcr)
{
case 0x01000201: //cpu to spu2 transfer
PSXDMA_LOG("*** DMA %c - mem2spu *** %x addr = %x size = %x\n", dmaNum, chcr, madr, bcr);
PSXDMA_LOG("*** DMA %c - mem2spu *** %x addr = %x size = %x", dmaNum, chcr, madr, bcr);
spu2WriteFunc((u16 *)iopPhysMem(madr), size*2);
break;
case 0x01000200: //spu2 to cpu transfer
PSXDMA_LOG("*** DMA %c - spu2mem *** %x addr = %x size = %x\n", dmaNum, chcr, madr, bcr);
PSXDMA_LOG("*** DMA %c - spu2mem *** %x addr = %x size = %x", dmaNum, chcr, madr, bcr);
spu2ReadFunc((u16 *)iopPhysMem(madr), size*2);
psxCpu->Clear(spuCore ? HW_DMA7_MADR : HW_DMA4_MADR, size);
break;
default:
Console::Error("*** DMA %c - SPU unknown *** %x addr = %x size = %x\n", params dmaNum, chcr, madr, bcr);
Console::Error("*** DMA %c - SPU unknown *** %x addr = %x size = %x", params dmaNum, chcr, madr, bcr);
break;
}
}
@ -97,7 +97,7 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr)
{
u32 *mem = (u32 *)iopPhysMem(madr);
PSXDMA_LOG("*** DMA 6 - OT *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
PSXDMA_LOG("*** DMA 6 - OT *** %lx addr = %lx size = %lx", chcr, madr, bcr);
if (chcr == 0x11000002) {
while (bcr--) {
@ -107,7 +107,7 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr)
mem++; *mem = 0xffffff;
} else {
// Unknown option
PSXDMA_LOG("*** DMA 6 - OT unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
PSXDMA_LOG("*** DMA 6 - OT unknown *** %lx addr = %lx size = %lx", chcr, madr, bcr);
}
HW_DMA6_CHCR &= ~0x01000000;
psxDmaInterrupt(6);
@ -129,7 +129,7 @@ int psxDma7Interrupt()
extern int eesifbusy[2];
void psxDma9(u32 madr, u32 bcr, u32 chcr)
{
SIF_LOG("IOP: dmaSIF0 chcr = %lx, madr = %lx, bcr = %lx, tadr = %lx\n", chcr, madr, bcr, HW_DMA9_TADR);
SIF_LOG("IOP: dmaSIF0 chcr = %lx, madr = %lx, bcr = %lx, tadr = %lx", chcr, madr, bcr, HW_DMA9_TADR);
iopsifbusy[0] = 1;
psHu32(0x1000F240) |= 0x2000;
@ -142,7 +142,7 @@ void psxDma9(u32 madr, u32 bcr, u32 chcr)
}
void psxDma10(u32 madr, u32 bcr, u32 chcr) {
SIF_LOG("IOP: dmaSIF1 chcr = %lx, madr = %lx, bcr = %lx\n", chcr, madr, bcr);
SIF_LOG("IOP: dmaSIF1 chcr = %lx, madr = %lx, bcr = %lx", chcr, madr, bcr);
iopsifbusy[1] = 1;
psHu32(0x1000F240) |= 0x4000;
@ -163,17 +163,17 @@ void psxDma8(u32 madr, u32 bcr, u32 chcr) {
switch (chcr & 0x01000201) {
case 0x01000201: //cpu to dev9 transfer
PSXDMA_LOG("*** DMA 8 - DEV9 mem2dev9 *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
PSXDMA_LOG("*** DMA 8 - DEV9 mem2dev9 *** %lx addr = %lx size = %lx", chcr, madr, bcr);
DEV9writeDMA8Mem((u32*)iopPhysMem(madr), size);
break;
case 0x01000200: //dev9 to cpu transfer
PSXDMA_LOG("*** DMA 8 - DEV9 dev9mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
PSXDMA_LOG("*** DMA 8 - DEV9 dev9mem *** %lx addr = %lx size = %lx", chcr, madr, bcr);
DEV9readDMA8Mem((u32*)iopPhysMem(madr), size);
break;
default:
PSXDMA_LOG("*** DMA 8 - DEV9 unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
PSXDMA_LOG("*** DMA 8 - DEV9 unknown *** %lx addr = %lx size = %lx", chcr, madr, bcr);
break;
}
HW_DMA8_CHCR &= ~0x01000000;

492
pcsx2/IopHw.cpp
View File

File diff suppressed because it is too large Load Diff

14
pcsx2/IopMem.cpp
View File

@ -156,7 +156,7 @@ u8 iopMemRead8(u32 mem)
{
if (t == 0x1000)
return DEV9read8(mem);
PSXMEM_LOG("err lb %8.8lx\n", mem);
PSXMEM_LOG("err lb %8.8lx", mem);
return 0;
}
}
@ -200,7 +200,7 @@ u16 iopMemRead16(u32 mem)
ret = psxHu16(mem);
break;
}
SIF_LOG("Sif reg read %x value %x\n", mem, ret);
SIF_LOG("Sif reg read %x value %x", mem, ret);
return ret;
}
return *(const u16 *)(p + (mem & 0xffff));
@ -211,7 +211,7 @@ u16 iopMemRead16(u32 mem)
return SPU2read(mem);
if (t == 0x1000)
return DEV9read16(mem);
PSXMEM_LOG("err lh %8.8lx\n", mem);
PSXMEM_LOG("err lh %8.8lx", mem);
return 0;
}
}
@ -261,7 +261,7 @@ u32 iopMemRead32(u32 mem)
ret = psxHu32(mem);
break;
}
SIF_LOG("Sif reg read %x value %x\n", mem, ret);
SIF_LOG("Sif reg read %x value %x", mem, ret);
return ret;
}
return *(const u32 *)(p + (mem & 0xffff));
@ -311,7 +311,7 @@ void iopMemWrite8(u32 mem, u8 value)
{
DEV9write8(mem, value); return;
}
PSXMEM_LOG("err sb %8.8lx = %x\n", mem, value);
PSXMEM_LOG("err sb %8.8lx = %x", mem, value);
}
}
}
@ -374,7 +374,7 @@ void iopMemWrite16(u32 mem, u16 value)
if (t == 0x1000) {
DEV9write16(mem, value); return;
}
PSXMEM_LOG("err sh %8.8lx = %x\n", mem, value);
PSXMEM_LOG("err sh %8.8lx = %x", mem, value);
}
}
}
@ -403,7 +403,7 @@ void iopMemWrite32(u32 mem, u32 value)
{
if (t == 0x1d00)
{
MEM_LOG("iop Sif reg write %x value %x\n", mem, value);
MEM_LOG("iop Sif reg write %x value %x", mem, value);
switch (mem & 0xf0)
{
case 0x00: // EE write path (EE/IOP readable)

18
pcsx2/IopSio2.cpp
View File

@ -60,13 +60,13 @@ void sio2Reset() {
}
u32 sio2_getRecv1() {
PAD_LOG("Reading Recv1 = %x\n",sio2.packet.recvVal1);
PAD_LOG("Reading Recv1 = %x",sio2.packet.recvVal1);
return sio2.packet.recvVal1;
}
u32 sio2_getRecv2() {
PAD_LOG("Reading Recv2 = %x\n",0xF);
PAD_LOG("Reading Recv2 = %x",0xF);
return 0xf;
}//0, 0x10, 0x20, 0x10 | 0x20; bits 4 & 5
@ -75,7 +75,7 @@ u32 sio2_getRecv3() {
if(sio2.packet.recvVal3 == 0x8C || sio2.packet.recvVal3 == 0x8b ||
sio2.packet.recvVal3 == 0x83)
{
PAD_LOG("Reading Recv3 = %x\n",sio2.packet.recvVal3);
PAD_LOG("Reading Recv3 = %x",sio2.packet.recvVal3);
sio.packetsize = sio2.packet.recvVal3;
sio2.packet.recvVal3 = 0; // Reset
@ -83,7 +83,7 @@ u32 sio2_getRecv3() {
}
else
{
PAD_LOG("Reading Recv3 = %x\n",sio.packetsize << 16);
PAD_LOG("Reading Recv3 = %x",sio.packetsize << 16);
return sio.packetsize << 16;
}
@ -103,7 +103,7 @@ void sio2_setSend3(u32 index, u32 value)
// for (i=0; i<4; i++){PAD_LOG("0x%08X ", sio2.packet.sendArray2[i]);}PAD_LOG("\n");
// for (i=0; i<8; i++){PAD_LOG("0x%08X ", sio2.packet.sendArray3[i]);}PAD_LOG("\n");
// for ( ; i<16; i++){PAD_LOG("0x%08X ", sio2.packet.sendArray3[i]);}PAD_LOG("\n");
PAD_LOG("[%d] : 0x%08X\n", index,sio2.packet.sendArray3[index]);
PAD_LOG("[%d] : 0x%08X", index,sio2.packet.sendArray3[index]);
// }
} //0->15
@ -148,7 +148,7 @@ void sio2_serialIn(u8 value){
ctrl |= (sio2.packet.sendArray3[sio2.cmdport] & 1) << 13;
//sioWriteCtrl16(SIO_RESET);
sioWriteCtrl16(ctrl);
PSXDMA_LOG("sio2_fifoIn: ctrl = %x, cmdlength = %x, cmdport = %d (%x)\n", ctrl, sio2.cmdlength, sio2.cmdport, sio2.packet.sendArray3[sio2.cmdport]);
PSXDMA_LOG("sio2_fifoIn: ctrl = %x, cmdlength = %x, cmdport = %d (%x)", ctrl, sio2.cmdlength, sio2.cmdport, sio2.packet.sendArray3[sio2.cmdport]);
sio2.cmdport++;
}
@ -175,7 +175,7 @@ void sio2_fifoIn(u8 value){
ctrl |= (sio2.packet.sendArray3[sio2.cmdport] & 1) << 13;
//sioWriteCtrl16(SIO_RESET);
sioWriteCtrl16(ctrl);
PSXDMA_LOG("sio2_fifoIn: ctrl = %x, cmdlength = %x, cmdport = %d (%x)\n", ctrl, sio2.cmdlength, sio2.cmdport, sio2.packet.sendArray3[sio2.cmdport]);
PSXDMA_LOG("sio2_fifoIn: ctrl = %x, cmdlength = %x, cmdport = %d (%x)", ctrl, sio2.cmdlength, sio2.cmdport, sio2.packet.sendArray3[sio2.cmdport]);
sio2.cmdport++;
}
@ -214,7 +214,7 @@ void SaveState::sio2Freeze()
void psxDma11(u32 madr, u32 bcr, u32 chcr) {
unsigned int i, j;
int size = (bcr >> 16) * (bcr & 0xffff);
PSXDMA_LOG("*** DMA 11 - SIO2 in *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
PSXDMA_LOG("*** DMA 11 - SIO2 in *** %lx addr = %lx size = %lx", chcr, madr, bcr);
if (chcr != 0x01000201) return;
@ -243,7 +243,7 @@ void psxDMA11Interrupt()
void psxDma12(u32 madr, u32 bcr, u32 chcr) {
int size = ((bcr >> 16) * (bcr & 0xFFFF)) * 4;
PSXDMA_LOG("*** DMA 12 - SIO2 out *** %lx addr = %lx size = %lx\n", chcr, madr, size);
PSXDMA_LOG("*** DMA 12 - SIO2 out *** %lx addr = %lx size = %lx", chcr, madr, size);
if (chcr != 0x41000200) return;

12
pcsx2/Mdec.cpp
View File

@ -156,7 +156,7 @@ void mdecInit(void) {
void mdecWrite0(u32 data) {
CDR_LOG("mdec0 write %lx\n", data);
CDR_LOG("mdec0 write %lx", data);
mdec.command = data;
if ((data&0xf5ff0000)==0x30000000) {
@ -165,7 +165,7 @@ void mdecWrite0(u32 data) {
}
void mdecWrite1(u32 data) {
CDR_LOG("mdec1 write %lx\n", data);
CDR_LOG("mdec1 write %lx", data);
if (data&0x80000000) { // mdec reset
round_init();
@ -174,14 +174,14 @@ void mdecWrite1(u32 data) {
}
u32 mdecRead0(void) {
CDR_LOG("mdec0 read %lx\n", mdec.command);
CDR_LOG("mdec0 read %lx", mdec.command);
return mdec.command;
}
u32 mdecRead1(void) {
#ifdef CDR_LOG
CDR_LOG("mdec1 read %lx\n", mdec.status);
CDR_LOG("mdec1 read %lx", mdec.status);
#endif
return mdec.status;
}
@ -190,7 +190,7 @@ void psxDma0(u32 adr, u32 bcr, u32 chcr) {
int cmd = mdec.command;
int size;
CDR_LOG("DMA0 %lx %lx %lx\n", adr, bcr, chcr);
CDR_LOG("DMA0 %lx %lx %lx", adr, bcr, chcr);
if (chcr!=0x01000201) return;
@ -214,7 +214,7 @@ void psxDma1(u32 adr, u32 bcr, u32 chcr) {
unsigned short *image;
int size;
CDR_LOG("DMA1 %lx %lx %lx (cmd = %lx)\n", adr, bcr, chcr, mdec.command);
CDR_LOG("DMA1 %lx %lx %lx (cmd = %lx)", adr, bcr, chcr, mdec.command);
if (chcr!=0x01000200) return;

26
pcsx2/Memory.cpp
View File

@ -71,7 +71,7 @@ void memSetUserMode() {
u16 ba0R16(u32 mem)
{
//MEM_LOG("ba00000 Memory read16 address %x\n", mem);
//MEM_LOG("ba00000 Memory read16 address %x", mem);
if (mem == 0x1a000006) {
static int ba6;
@ -259,7 +259,7 @@ mem8_t __fastcall _ext_memRead8 (u32 mem)
}
}
MEM_LOG("Unknown Memory Read8 from address %8.8x\n", mem);
MEM_LOG("Unknown Memory Read8 from address %8.8x", mem);
cpuTlbMissR(mem, cpuRegs.branch);
return 0;
}
@ -274,7 +274,7 @@ mem16_t __fastcall _ext_memRead16(u32 mem)
case 2: // psh
return psxHwRead16(mem);
case 4: // b80
MEM_LOG("b800000 Memory read16 address %x\n", mem);
MEM_LOG("b800000 Memory read16 address %x", mem);
return 0;
case 5: // ba0
return ba0R16(mem);
@ -291,7 +291,7 @@ mem16_t __fastcall _ext_memRead16(u32 mem)
case 8: // spu2
return SPU2read(mem);
}
MEM_LOG("Unknown Memory read16 from address %8.8x\n", mem);
MEM_LOG("Unknown Memory read16 from address %8.8x", mem);
cpuTlbMissR(mem, cpuRegs.branch);
return 0;
}
@ -313,7 +313,7 @@ mem32_t __fastcall _ext_memRead32(u32 mem)
}
}
MEM_LOG("Unknown Memory read32 from address %8.8x (Status=%8.8x)\n", mem, cpuRegs.CP0.n.Status.val);
MEM_LOG("Unknown Memory read32 from address %8.8x (Status=%8.8x)", mem, cpuRegs.CP0.n.Status.val);
cpuTlbMissR(mem, cpuRegs.branch);
return 0;
}
@ -327,7 +327,7 @@ void __fastcall _ext_memRead64(u32 mem, mem64_t *out)
*out = gsRead64(mem); return;
}
MEM_LOG("Unknown Memory read64 from address %8.8x\n", mem);
MEM_LOG("Unknown Memory read64 from address %8.8x", mem);
cpuTlbMissR(mem, cpuRegs.branch);
}
@ -343,7 +343,7 @@ void __fastcall _ext_memRead128(u32 mem, mem128_t *out)
out[1] = gsRead64(mem+8); return;
}
MEM_LOG("Unknown Memory read128 from address %8.8x\n", mem);
MEM_LOG("Unknown Memory read128 from address %8.8x", mem);
cpuTlbMissR(mem, cpuRegs.branch);
}
@ -366,7 +366,7 @@ void __fastcall _ext_memWrite8 (u32 mem, u8 value)
return;
}
MEM_LOG("Unknown Memory write8 to address %x with data %2.2x\n", mem, value);
MEM_LOG("Unknown Memory write8 to address %x with data %2.2x", mem, value);
cpuTlbMissW(mem, cpuRegs.branch);
}
template<int p>
@ -379,7 +379,7 @@ void __fastcall _ext_memWrite16(u32 mem, u16 value)
case 2: // psh
psxHwWrite16(mem, value); return;
case 5: // ba0
MEM_LOG("ba00000 Memory write16 to address %x with data %x\n", mem, value);
MEM_LOG("ba00000 Memory write16 to address %x with data %x", mem, value);
return;
case 6: // gsm
gsWrite16(mem, value); return;
@ -390,7 +390,7 @@ void __fastcall _ext_memWrite16(u32 mem, u16 value)
case 8: // spu2
SPU2write(mem, value); return;
}
MEM_LOG("Unknown Memory write16 to address %x with data %4.4x\n", mem, value);
MEM_LOG("Unknown Memory write16 to address %x with data %4.4x", mem, value);
cpuTlbMissW(mem, cpuRegs.branch);
}
@ -407,7 +407,7 @@ void __fastcall _ext_memWrite32(u32 mem, u32 value)
Console::WriteLn("DEV9 write32 %8.8lx: %8.8lx", params mem & ~0xa4000000, value);
return;
}
MEM_LOG("Unknown Memory write32 to address %x with data %8.8x\n", mem, value);
MEM_LOG("Unknown Memory write32 to address %x with data %8.8x", mem, value);
cpuTlbMissW(mem, cpuRegs.branch);
}
@ -423,7 +423,7 @@ void __fastcall _ext_memWrite64(u32 mem, const u64* value)
// gsWrite64(mem & ~0xa0000000, *value); return;
}*/
MEM_LOG("Unknown Memory write64 to address %x with data %8.8x_%8.8x\n", mem, (u32)(*value>>32), (u32)*value);
MEM_LOG("Unknown Memory write64 to address %x with data %8.8x_%8.8x", mem, (u32)(*value>>32), (u32)*value);
cpuTlbMissW(mem, cpuRegs.branch);
}
@ -440,7 +440,7 @@ void __fastcall _ext_memWrite128(u32 mem, const u64 *value)
// gsWrite64(mem+8, value[1]); return;
}*/
MEM_LOG("Unknown Memory write128 to address %x with data %8.8x_%8.8x_%8.8x_%8.8x\n", mem, ((u32*)value)[3], ((u32*)value)[2], ((u32*)value)[1], ((u32*)value)[0]);
MEM_LOG("Unknown Memory write128 to address %x with data %8.8x_%8.8x_%8.8x_%8.8x", mem, ((u32*)value)[3], ((u32*)value)[2], ((u32*)value)[1], ((u32*)value)[0]);
cpuTlbMissW(mem, cpuRegs.branch);
}

14
pcsx2/R3000A.cpp
View File

@ -75,7 +75,7 @@ void psxShutdown() {
}
void psxException(u32 code, u32 bd) {
// PSXCPU_LOG("psxException %x: %x, %x\n", code, psxHu32(0x1070), psxHu32(0x1074));
// PSXCPU_LOG("psxException %x: %x, %x", code, psxHu32(0x1070), psxHu32(0x1074));
//Console::WriteLn("!! psxException %x: %x, %x", params code, psxHu32(0x1070), psxHu32(0x1074));
// Set the Cause
psxRegs.CP0.n.Cause &= ~0x7f;
@ -84,7 +84,7 @@ void psxException(u32 code, u32 bd) {
// Set the EPC & PC
if (bd)
{
PSXCPU_LOG("bd set\n");
PSXCPU_LOG("bd set");
psxRegs.CP0.n.Cause|= 0x80000000;
psxRegs.CP0.n.EPC = (psxRegs.pc - 4);
}
@ -111,7 +111,7 @@ void psxException(u32 code, u32 bd) {
case 0xa0:
if (call != 0x28 && call != 0xe)
PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
if (biosA0[call])
biosA0[call]();
@ -119,14 +119,14 @@ void psxException(u32 code, u32 bd) {
case 0xb0:
if (call != 0x17 && call != 0xb)
PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
if (biosB0[call])
biosB0[call]();
break;
case 0xc0:
PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
if (biosC0[call])
biosC0[call]();
@ -248,7 +248,7 @@ void psxBranchTest()
if ((psxRegs.CP0.n.Status & 0xFE01) >= 0x401)
{
PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
PSXCPU_LOG("Interrupt: %x %x", psxHu32(0x1070), psxHu32(0x1074));
psxException(0, 0);
iopBranchAction = true;
}
@ -278,6 +278,6 @@ void iopTestIntc()
void psxExecuteBios() {
/* while (psxRegs.pc != 0x80030000)
psxCpu->ExecuteBlock();
PSX_LOG("*BIOS END*\n");
PSX_LOG("*BIOS END*");
*/
}

14
pcsx2/R3000AInterpreter.cpp
View File

@ -291,7 +291,7 @@ void zeroEx()
pc = psxRegs.GPR.n.ra;
while (psxRegs.pc != pc) psxCpu->ExecuteBlock();
PSXBIOS_LOG("%s: %s (%x) END\n", lib, fname == NULL ? "unknown" : fname, code);*/
PSXBIOS_LOG("%s: %s (%x) END", lib, fname == NULL ? "unknown" : fname, code);*/
#endif
}
@ -305,7 +305,7 @@ char* getName(char *file, u32 addr){
name[0]=0;
else{
while (!feof(f)){
fscanf(f, "%08X %s\n", &a, name);
fscanf(f, "%08X %s", &a, name);
if (a==addr)break;
}
fclose(f);
@ -324,13 +324,13 @@ void spyFunctions(){
if (strncmp("__push_params", name, 13)==0){
PAD_LOG(PSXM(psxRegs.GPR.n.a0), psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
}else{
PAD_LOG("secrman: %s (ra=%06X cycle=%d)\n", name, psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}}else
PAD_LOG("secrman: %s (ra=%06X cycle=%d)", name, psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}}else
if (strcmp("mcman", PSXM(iii->name))==0){
PAD_LOG("mcman: %s (ra=%06X cycle=%d)\n", getName("mcman.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}else
PAD_LOG("mcman: %s (ra=%06X cycle=%d)", getName("mcman.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}else
if (strcmp("padman", PSXM(iii->name))==0){
PAD_LOG("padman: %s (ra=%06X cycle=%d)\n", getName("padman.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}else
PAD_LOG("padman: %s (ra=%06X cycle=%d)", getName("padman.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}else
if (strcmp("sio2man", PSXM(iii->name))==0){
PAD_LOG("sio2man: %s (ra=%06X cycle=%d)\n", getName("sio2man.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}
PAD_LOG("sio2man: %s (ra=%06X cycle=%d)", getName("sio2man.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}
break;
}
}
@ -381,7 +381,7 @@ static __forceinline void execI()
psxRegs.code = iopMemRead32(psxRegs.pc);
//if( (psxRegs.pc >= 0x1200 && psxRegs.pc <= 0x1400) || (psxRegs.pc >= 0x0b40 && psxRegs.pc <= 0x1000))
PSXCPU_LOG("%s\n", disR3000AF(psxRegs.code, psxRegs.pc));
PSXCPU_LOG("%s", disR3000AF(psxRegs.code, psxRegs.pc));
psxRegs.pc+= 4;
psxRegs.cycle++;

12
pcsx2/R5900OpcodeImpl.cpp
View File

@ -130,12 +130,12 @@ void COP2()
//std::string disOut;
//disR5900Fasm(disOut, cpuRegs.code, cpuRegs.pc);
//VU0_LOG("%s\n", disOut.c_str());
//VU0_LOG("%s", disOut.c_str());
Int_COP2PrintTable[_Rs_]();
}
void Unknown() {
CPU_LOG("%8.8lx: Unknown opcode called\n", cpuRegs.pc);
CPU_LOG("%8.8lx: Unknown opcode called", cpuRegs.pc);
}
void MMI_Unknown() { Console::Notice("Unknown MMI opcode called"); }
@ -758,7 +758,7 @@ int __Deci2Call(int call, u32 *addr)
if( addr != NULL )
{
deci2addr = (u32*)PSM(addr[1]);
BIOS_LOG("deci2open: %x,%x,%x,%x\n",
BIOS_LOG("deci2open: %x,%x,%x,%x",
addr[3], addr[2], addr[1], addr[0]);
deci2handler = addr[2];
}
@ -778,7 +778,7 @@ int __Deci2Call(int call, u32 *addr)
if( addr != NULL )
sprintf( reqaddr, "%x %x %x %x", addr[3], addr[2], addr[1], addr[0] );
BIOS_LOG("deci2reqsend: %s: deci2addr: %x,%x,%x,buf=%x %x,%x,len=%x,%x\n",
BIOS_LOG("deci2reqsend: %s: deci2addr: %x,%x,%x,buf=%x %x,%x,len=%x,%x",
(( addr == NULL ) ? "NULL" : reqaddr),
deci2addr[7], deci2addr[6], deci2addr[5], deci2addr[4],
deci2addr[3], deci2addr[2], deci2addr[1], deci2addr[0]);
@ -830,7 +830,7 @@ void SYSCALL()
else
call = cpuRegs.GPR.n.v1.UC[0];
BIOS_LOG("Bios call: %s (%x)\n", bios[call], call);
BIOS_LOG("Bios call: %s (%x)", bios[call], call);
if (call == 0x7c)
{
@ -856,7 +856,7 @@ void SYSCALL()
addr = cpuRegs.GPR.n.a0.UL[0] + n_transfer * sizeof(t_sif_dma_transfer);
dmat = (t_sif_dma_transfer*)PSM(addr);
BIOS_LOG("bios_%s: n_transfer=%d, size=%x, attr=%x, dest=%x, src=%x\n",
BIOS_LOG("bios_%s: n_transfer=%d, size=%x, attr=%x, dest=%x, src=%x",
bios[cpuRegs.GPR.n.v1.UC[0]], n_transfer,
dmat->size, dmat->attr,
dmat->dest, dmat->src);

22
pcsx2/SPR.cpp
View File

@ -35,7 +35,7 @@ void sprInit() {
//__forceinline static void SPR0transfer(u32 *data, int size) {
///* while (size > 0) {
// SPR_LOG("SPR1transfer: %x\n", *data);
// SPR_LOG("SPR1transfer: %x", *data);
// data++; size--;
// }*/
// size <<= 2;
@ -54,11 +54,11 @@ static void TestClearVUs(u32 madr, u32 size)
{
if( madr >= 0x11000000 ) {
if( madr < 0x11004000 ) {
DbgCon::Notice("scratch pad clearing vu0\n");
DbgCon::Notice("scratch pad clearing vu0");
CpuVU0.Clear(madr&0xfff, size);
}
else if( madr >= 0x11008000 && madr < 0x1100c000 ) {
DbgCon::Notice("scratch pad clearing vu1\n");
DbgCon::Notice("scratch pad clearing vu1");
CpuVU1.Clear(madr&0x3fff, size);
}
}
@ -106,7 +106,7 @@ void _SPR0interleave() {
u32 *pMem;
if(tqwc == 0) tqwc = qwc;
//Console::WriteLn("dmaSPR0 interleave");
SPR_LOG("SPR0 interleave size=%d, tqwc=%d, sqwc=%d, addr=%lx sadr=%lx\n",
SPR_LOG("SPR0 interleave size=%d, tqwc=%d, sqwc=%d, addr=%lx sadr=%lx",
spr0->qwc, tqwc, sqwc, spr0->madr, spr0->sadr);
while (qwc > 0) {
@ -173,7 +173,7 @@ static __forceinline void _dmaSPR0() {
spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
spr0->madr = ptag[1]; //MADR = ADDR field
SPR_LOG("spr0 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx\n",
SPR_LOG("spr0 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
ptag[1], ptag[0], spr0->qwc, id, spr0->madr, spr0->sadr);
if ((psHu32(DMAC_CTRL) & 0x30) == 0x20) { // STS == fromSPR
@ -217,7 +217,7 @@ static __forceinline void _dmaSPR0() {
spr0->qwc = 0;
return;
}
SPR_LOG("spr0 dmaChain complete %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx\n",
SPR_LOG("spr0 dmaChain complete %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
ptag[1], ptag[0], spr0->qwc, id, spr0->madr);
//CPU_INT(8, cycles);
} else { // Interleave Mode
@ -261,7 +261,7 @@ void SPRFROMinterrupt()
void dmaSPR0() { // fromSPR
SPR_LOG("dmaSPR0 chcr = %lx, madr = %lx, qwc = %lx, sadr = %lx\n",
SPR_LOG("dmaSPR0 chcr = %lx, madr = %lx, qwc = %lx, sadr = %lx",
spr0->chcr, spr0->madr, spr0->qwc, spr0->sadr);
if ((spr0->chcr & 0xc) == 0x4 && spr0->qwc == 0){
@ -316,7 +316,7 @@ void _SPR1interleave() {
int cycles = 0;
u32 *pMem;
if(tqwc == 0) tqwc = qwc;
SPR_LOG("SPR1 interleave size=%d, tqwc=%d, sqwc=%d, addr=%lx sadr=%lx\n",
SPR_LOG("SPR1 interleave size=%d, tqwc=%d, sqwc=%d, addr=%lx sadr=%lx",
spr1->qwc, tqwc, sqwc, spr1->madr, spr1->sadr);
while (qwc > 0) {
@ -380,14 +380,14 @@ void _dmaSPR1() { // toSPR work function
SPR1transfer(ptag, 4); //Transfer Tag
}
SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n",
SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx",
ptag[1], ptag[0], spr1->qwc, id, spr1->madr);
done = hwDmacSrcChain(spr1, id);
SPR1chain(); //Transfers the data set by the switch
if (spr1->chcr & 0x80 && ptag[0] >> 31) { //Check TIE bit of CHCR and IRQ bit of tag
SPR_LOG("dmaIrq Set\n");
SPR_LOG("dmaIrq Set");
//Console::WriteLn("SPR1 TIE");
spr1->qwc = 0;
@ -410,7 +410,7 @@ void _dmaSPR1() { // toSPR work function
void dmaSPR1() { // toSPR
SPR_LOG("dmaSPR1 chcr = 0x%x, madr = 0x%x, qwc = 0x%x\n"
" tadr = 0x%x, sadr = 0x%x\n",
" tadr = 0x%x, sadr = 0x%x",
spr1->chcr, spr1->madr, spr1->qwc,
spr1->tadr, spr1->sadr);

68
pcsx2/Sif.cpp
View File

@ -93,7 +93,7 @@ static __forceinline void SIF0write(u32 *from, int words)
}*/
sif0.fifoSize += words;
SIF_LOG(" SIF0 + %d = %d (pos=%d)\n", words, sif0.fifoSize, sif0.fifoWritePos);
SIF_LOG(" SIF0 + %d = %d (pos=%d)", words, sif0.fifoSize, sif0.fifoWritePos);
}
static __forceinline void SIF0read(u32 *to, int words)
@ -115,7 +115,7 @@ static __forceinline void SIF0read(u32 *to, int words)
}*/
sif0.fifoSize -= words;
SIF_LOG(" SIF0 - %d = %d (pos=%d)\n", words, sif0.fifoSize, sif0.fifoReadPos);
SIF_LOG(" SIF0 - %d = %d (pos=%d)", words, sif0.fifoSize, sif0.fifoReadPos);
}
__forceinline void SIF1write(u32 *from, int words)
@ -137,7 +137,7 @@ __forceinline void SIF1write(u32 *from, int words)
}*/
sif1.fifoSize += words;
SIF_LOG(" SIF1 + %d = %d (pos=%d)\n", words, sif1.fifoSize, sif1.fifoWritePos);
SIF_LOG(" SIF1 + %d = %d (pos=%d)", words, sif1.fifoSize, sif1.fifoWritePos);
}
static __forceinline void SIF1read(u32 *to, int words)
@ -159,7 +159,7 @@ static __forceinline void SIF1read(u32 *to, int words)
}*/
sif1.fifoSize -= words;
SIF_LOG(" SIF1 - %d = %d (pos=%d)\n", words, sif1.fifoSize, sif1.fifoReadPos);
SIF_LOG(" SIF1 - %d = %d (pos=%d)", words, sif1.fifoSize, sif1.fifoReadPos);
}
__forceinline void SIF0Dma()
@ -168,7 +168,7 @@ __forceinline void SIF0Dma()
int notDone = 1;
int cycles = 0, psxCycles = 0;
SIF_LOG("SIF0 DMA start...\n");
SIF_LOG("SIF0 DMA start...");
do
{
@ -185,7 +185,7 @@ __forceinline void SIF0Dma()
// Note.. add normal mode here
if (sif0.sifData.data & 0xC0000000) // If NORMAL mode or end of CHAIN, or interrupt then stop DMA
{
SIF_LOG(" IOP SIF Stopped\n");
SIF_LOG(" IOP SIF Stopped");
// Stop & signal interrupts on IOP
//HW_DMA9_CHCR &= ~0x01000000; //reset TR flag
@ -217,18 +217,18 @@ __forceinline void SIF0Dma()
sif0.counter = sif0.sifData.words & 0xFFFFFF;
notDone = 1;
SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)\n", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.sifData.words, sif0.sifData.data);
SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.sifData.words, sif0.sifData.data);
if(sif0.sifData.data & 0x40000000)
SIF_LOG(" END\n");
SIF_LOG(" END");
else
SIF_LOG(" CNT %08X, %08X\n", sif0.sifData.data, sif0.sifData.words);
SIF_LOG(" CNT %08X, %08X", sif0.sifData.data, sif0.sifData.words);
}
}
else // There's some data ready to transfer into the fifo..
{
int wTransfer = min(sif0.counter, FIFO_SIF0_W-sif0.fifoSize); // HW_DMA9_BCR >> 16;
SIF_LOG("+++++++++++ %lX of %lX\n", wTransfer, sif0.counter /*(HW_DMA9_BCR >> 16)*/ );
SIF_LOG("+++++++++++ %lX of %lX", wTransfer, sif0.counter /*(HW_DMA9_BCR >> 16)*/ );
SIF0write((u32*)iopPhysMem(HW_DMA9_MADR), wTransfer);
HW_DMA9_MADR += wTransfer << 2;
@ -245,7 +245,7 @@ __forceinline void SIF0Dma()
{
int size = sif0dma->qwc;
if ((psHu32(DMAC_CTRL) & 0x30) == 0x10) { // STS == fromSIF0
SIF_LOG("SIF0 stall control\n");
SIF_LOG("SIF0 stall control");
}
if(size > 0) // If we're reading something continue to do so
{
@ -253,8 +253,8 @@ __forceinline void SIF0Dma()
{*/
int readSize = min(size, (sif0.fifoSize>>2));
//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X\n", readSize, sif0dma->madr);
SIF_LOG("----------- %lX of %lX\n", readSize << 2, size << 2 );
//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
SIF_LOG("----------- %lX of %lX", readSize << 2, size << 2 );
_dmaGetAddr(sif0dma, ptag, sif0dma->madr, 5);
@ -262,7 +262,7 @@ __forceinline void SIF0Dma()
// {
// int i;
// for(i = 0; i < readSize; ++i) {
// SIF_LOG("EE SIF0 read madr: %x %x %x %x\n", ((u32*)ptag)[4*i+0], ((u32*)ptag)[4*i+1], ((u32*)ptag)[4*i+2], ((u32*)ptag)[4*i+3]);
// SIF_LOG("EE SIF0 read madr: %x %x %x %x", ((u32*)ptag)[4*i+0], ((u32*)ptag)[4*i+1], ((u32*)ptag)[4*i+2], ((u32*)ptag)[4*i+3]);
// }
// }
@ -282,7 +282,7 @@ __forceinline void SIF0Dma()
if((sif0dma->chcr & 0x80000080) == 0x80000080) // Stop on tag IRQ
{
// Tag interrupt
SIF_LOG(" EE SIF interrupt\n");
SIF_LOG(" EE SIF interrupt");
//sif0dma->chcr &= ~0x100;
eesifbusy[0] = 0;
@ -293,7 +293,7 @@ __forceinline void SIF0Dma()
else if(sif0.end) // Stop on tag END
{
// End tag.
SIF_LOG(" EE SIF end\n");
SIF_LOG(" EE SIF end");
//sif0dma->chcr &= ~0x100;
//hwDmacIrq(5);
@ -305,7 +305,7 @@ __forceinline void SIF0Dma()
{
static PCSX2_ALIGNED16(u32 tag[4]);
SIF0read((u32*)&tag[0], 4); // Tag
SIF_LOG(" EE SIF read tag: %x %x %x %x\n", tag[0], tag[1], tag[2], tag[3]);
SIF_LOG(" EE SIF read tag: %x %x %x %x", tag[0], tag[1], tag[2], tag[3]);
sif0dma->qwc = (u16)tag[0];
sif0dma->madr = tag[1];
@ -314,7 +314,7 @@ __forceinline void SIF0Dma()
/*if ((sif0dma->chcr & 0x80) && (tag[0] >> 31)) {
Console::WriteLn("SIF0 TIE");
}*/
SIF_LOG(" EE SIF dest chain tag madr:%08X qwc:%04X id:%X irq:%d(%08X_%08X)\n", sif0dma->madr, sif0dma->qwc, (tag[0]>>28)&3, (tag[0]>>31)&1, tag[1], tag[0]);
SIF_LOG(" EE SIF dest chain tag madr:%08X qwc:%04X id:%X irq:%d(%08X_%08X)", sif0dma->madr, sif0dma->qwc, (tag[0]>>28)&3, (tag[0]>>31)&1, tag[1], tag[0]);
if ((psHu32(DMAC_CTRL) & 0x30) != 0 && ((tag[0]>>28)&3) == 0)
psHu32(DMAC_STADR) = sif0dma->madr + (sif0dma->qwc * 16);
@ -342,7 +342,7 @@ __forceinline void SIF1Dma()
{
if ((psHu32(DMAC_CTRL) & 0xC0) == 0xC0)
SIF_LOG("SIF1 stall control\n"); // STS == fromSIF1
SIF_LOG("SIF1 stall control"); // STS == fromSIF1
if(sif1dma->qwc == 0) // If there's no more to transfer
{
@ -351,7 +351,7 @@ __forceinline void SIF1Dma()
// Stop & signal interrupts on EE
//sif1dma->chcr &= ~0x100;
//hwDmacIrq(6);
SIF_LOG("EE SIF1 End %x\n", sif1.end);
SIF_LOG("EE SIF1 End %x", sif1.end);
eesifbusy[1] = 0;
notDone = 0;
CPU_INT(6, cycles*BIAS);
@ -377,33 +377,33 @@ __forceinline void SIF1Dma()
switch(id)
{
case 0: // refe
SIF_LOG(" REFE %08X\n", ptag[1]);
SIF_LOG(" REFE %08X", ptag[1]);
sif1.end = 1;
sif1dma->madr = ptag[1];
sif1dma->tadr += 16;
break;
case 1: // cnt
SIF_LOG(" CNT\n");
SIF_LOG(" CNT");
sif1dma->madr = sif1dma->tadr + 16;
sif1dma->tadr = sif1dma->madr + (sif1dma->qwc << 4);
break;
case 2: // next
SIF_LOG(" NEXT %08X\n", ptag[1]);
SIF_LOG(" NEXT %08X", ptag[1]);
sif1dma->madr = sif1dma->tadr + 16;
sif1dma->tadr = ptag[1];
break;
case 3: // ref
case 4: // refs
SIF_LOG(" REF %08X\n", ptag[1]);
SIF_LOG(" REF %08X", ptag[1]);
sif1dma->madr = ptag[1];
sif1dma->tadr += 16;
break;
case 7: // end
SIF_LOG(" END\n");
SIF_LOG(" END");
sif1.end = 1;
sif1dma->madr = sif1dma->tadr + 16;
sif1dma->tadr = sif1dma->madr + (sif1dma->qwc << 4);
@ -450,7 +450,7 @@ __forceinline void SIF1Dma()
if(readSize > sif1.fifoSize) readSize = sif1.fifoSize;
SIF_LOG(" IOP SIF doing transfer %04X to %08X\n", readSize, HW_DMA10_MADR);
SIF_LOG(" IOP SIF doing transfer %04X to %08X", readSize, HW_DMA10_MADR);
SIF1read((u32*)iopPhysMem(HW_DMA10_MADR), readSize);
psxCpu->Clear(HW_DMA10_MADR, readSize);
@ -466,7 +466,7 @@ __forceinline void SIF1Dma()
if(sif1.tagMode & 0x80) // Stop on tag IRQ
{
// Tag interrupt
SIF_LOG(" IOP SIF interrupt\n");
SIF_LOG(" IOP SIF interrupt");
//HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
//psxDmaInterrupt2(3);
iopsifbusy[1] = 0;
@ -478,7 +478,7 @@ __forceinline void SIF1Dma()
else if(sif1.tagMode & 0x40) // Stop on tag END
{
// End tag.
SIF_LOG(" IOP SIF end\n");
SIF_LOG(" IOP SIF end");
//HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
//psxDmaInterrupt2(3);
iopsifbusy[1] = 0;
@ -491,7 +491,7 @@ __forceinline void SIF1Dma()
{
struct sifData d;
SIF1read((u32*)&d, 4);
SIF_LOG(" IOP SIF dest chain tag madr:%08X wc:%04X id:%X irq:%d\n", d.data & 0xffffff, d.words, (d.data>>28)&7, (d.data>>31)&1);
SIF_LOG(" IOP SIF dest chain tag madr:%08X wc:%04X id:%X irq:%d", d.data & 0xffffff, d.words, (d.data>>28)&7, (d.data>>31)&1);
HW_DMA10_MADR = d.data & 0xffffff;
sif1.counter = d.words;
sif1.tagMode = (d.data >> 24) & 0xFF;
@ -527,11 +527,11 @@ __forceinline void EEsif1Interrupt() {
}
__forceinline void dmaSIF0() {
SIF_LOG("EE: dmaSIF0 chcr = %lx, madr = %lx, qwc = %lx, tadr = %lx\n",
SIF_LOG("EE: dmaSIF0 chcr = %lx, madr = %lx, qwc = %lx, tadr = %lx",
sif0dma->chcr, sif0dma->madr, sif0dma->qwc, sif0dma->tadr);
if (sif0.fifoReadPos != sif0.fifoWritePos) {
SIF_LOG("warning, sif0.fifoReadPos != sif0.fifoWritePos\n");
SIF_LOG("warning, sif0.fifoReadPos != sif0.fifoWritePos");
}
// if(sif0dma->qwc > 0 & (sif0dma->chcr & 0x4) == 0x4) {
// sif0dma->chcr &= ~4; //Halflife sets a QWC amount in chain mode, no tadr set.
@ -551,11 +551,11 @@ __forceinline void dmaSIF0() {
}
__forceinline void dmaSIF1() {
SIF_LOG("EE: dmaSIF1 chcr = %lx, madr = %lx, qwc = %lx, tadr = %lx\n",
SIF_LOG("EE: dmaSIF1 chcr = %lx, madr = %lx, qwc = %lx, tadr = %lx",
sif1dma->chcr, sif1dma->madr, sif1dma->qwc, sif1dma->tadr);
if (sif1.fifoReadPos != sif1.fifoWritePos) {
SIF_LOG("warning, sif1.fifoReadPos != sif1.fifoWritePos\n");
SIF_LOG("warning, sif1.fifoReadPos != sif1.fifoWritePos");
}
// if(sif1dma->qwc > 0 & (sif1dma->chcr & 0x4) == 0x4) {
@ -577,7 +577,7 @@ __forceinline void dmaSIF1() {
}
__forceinline void dmaSIF2() {
SIF_LOG("dmaSIF2 chcr = %lx, madr = %lx, qwc = %lx\n",
SIF_LOG("dmaSIF2 chcr = %lx, madr = %lx, qwc = %lx",
sif2dma->chcr, sif2dma->madr, sif2dma->qwc);
sif2dma->chcr&= ~0x100;

58
pcsx2/Sio.cpp
View File

@ -99,12 +99,12 @@ u8 sioRead8() {
}*/
}
}
//PAD_LOG("sio read8 ;ret = %x\n", ret);
//PAD_LOG("sio read8 ;ret = %x", ret);
return ret;
}
void SIO_CommandWrite(u8 value,int way) {
PAD_LOG("sio write8 %x\n", value);
PAD_LOG("sio write8 %x", value);
// PAD COMMANDS
switch (sio.padst) {
@ -149,7 +149,7 @@ void SIO_CommandWrite(u8 value,int way) {
sio.parp = 1;
switch (value) {
case 0x11: // RESET
PAD_LOG("RESET MEMORY CARD\n");
PAD_LOG("RESET MEMORY CARD");
sio.bufcount = 8;
memset8_obj<0xff>(sio.buf);
@ -166,7 +166,7 @@ void SIO_CommandWrite(u8 value,int way) {
sio.mcdst = 99;
sio2.packet.recvVal3 = 0x8c;
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x81: // COMMIT
sio.bufcount = 8;
@ -180,7 +180,7 @@ void SIO_CommandWrite(u8 value,int way) {
sio2.packet.recvVal1 = 0x1600; // Writing
else if(sio.mc_command==0x43) sio2.packet.recvVal1 = 0x1700; // Reading
}
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x21:
case 0x22:
@ -190,20 +190,20 @@ void SIO_CommandWrite(u8 value,int way) {
sio2.packet.recvVal3 = 0x8c;
sio.buf[8]=sio.terminator;
sio.buf[7]='+';
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x24:
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x25:
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x26:
sio.bufcount = 12; sio.mcdst = 99; sio2.packet.recvVal3 = 0x83;
memset8_obj<0xff>(sio.buf);
memcpy(&sio.buf[2], &mc_command_0x26, sizeof(mc_command_0x26));
sio.buf[12]=sio.terminator;
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x27:
case 0x28:
@ -212,7 +212,7 @@ void SIO_CommandWrite(u8 value,int way) {
memset8_obj<0xff>(sio.buf);
sio.buf[4]=sio.terminator;
sio.buf[3]='+';
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x42: // WRITE
case 0x43: // READ
@ -225,13 +225,13 @@ void SIO_CommandWrite(u8 value,int way) {
memset8_obj<0xff>(sio.buf);
sio.buf[133]=sio.terminator;
sio.buf[132]='+';
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0xf0:
case 0xf1:
case 0xf2:
sio.mcdst = 99;
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0xf3:
case 0xf7:
@ -239,23 +239,23 @@ void SIO_CommandWrite(u8 value,int way) {
memset8_obj<0xff>(sio.buf);
sio.buf[4]=sio.terminator;
sio.buf[3]='+';
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x52:
sio.rdwr = 1; memset8_obj<0xff>(sio.buf);
sio.buf[sio.bufcount]=sio.terminator; sio.buf[sio.bufcount-1]='+';
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
case 0x57:
sio.rdwr = 2; memset8_obj<0xff>(sio.buf);
sio.buf[sio.bufcount]=sio.terminator; sio.buf[sio.bufcount-1]='+';
MEMCARDS_LOG("MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
break;
default:
sio.mcdst = 0;
memset8_obj<0xff>(sio.buf);
sio.buf[sio.bufcount]=sio.terminator; sio.buf[sio.bufcount-1]='+';
MEMCARDS_LOG("Unknown MC(%d) command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("Unknown MC(%d) command 0x%02X", sio.GetMemcardIndex()+1, value);
}
sio.mc_command=value;
return;
@ -278,10 +278,10 @@ void SIO_CommandWrite(u8 value,int way) {
if (sio.parp==6)
{
if (sio_xor((u8 *)&sio.sector, 4) == value)
MEMCARDS_LOG("MC(%d) SET PAGE sio.sector 0x%04X\n",
MEMCARDS_LOG("MC(%d) SET PAGE sio.sector 0x%04X",
sio.GetMemcardIndex()+1, sio.sector);
else
MEMCARDS_LOG("MC(%d) SET PAGE XOR value ERROR 0x%02X != ^0x%02X\n",
MEMCARDS_LOG("MC(%d) SET PAGE XOR value ERROR 0x%02X != ^0x%02X",
sio.GetMemcardIndex()+1, value, sio_xor((u8 *)&sio.sector, 4));
}
break;
@ -291,7 +291,7 @@ void SIO_CommandWrite(u8 value,int way) {
if(sio.parp==2) {
sio.terminator = value;
sio.buf[4] = value;
MEMCARDS_LOG("MC(%d) SET TERMINATOR command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) SET TERMINATOR command 0x%02X", sio.GetMemcardIndex()+1, value);
}
break;
@ -305,7 +305,7 @@ void SIO_CommandWrite(u8 value,int way) {
//if(value == 0) sio.buf[4] = 0xFF;
sio.buf[4] = 0x55;
MEMCARDS_LOG("MC(%d) GET TERMINATOR command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) GET TERMINATOR command 0x%02X", sio.GetMemcardIndex()+1, value);
}
break;
// WRITE DATA
@ -315,12 +315,12 @@ void SIO_CommandWrite(u8 value,int way) {
memset8_obj<0xff>(sio.buf);
sio.buf[sio.bufcount-1]='+';
sio.buf[sio.bufcount]=sio.terminator;
MEMCARDS_LOG("MC(%d) WRITE command 0x%02X\n\n\n\n\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) WRITE command 0x%02X\n\n\n\n", sio.GetMemcardIndex()+1, value);
}
else
if ((sio.parp>2) && (sio.parp<sio.bufcount-2)) {
sio.buf[sio.parp]=value;
//MEMCARDS_LOG("MC(%d) WRITING 0x%02X\n", sio.GetMemcardIndex()+1, value);
//MEMCARDS_LOG("MC(%d) WRITING 0x%02X", sio.GetMemcardIndex()+1, value);
} else
if (sio.parp==sio.bufcount-2) {
if (sio_xor(&sio.buf[3], sio.bufcount-5)==value) {
@ -328,7 +328,7 @@ void SIO_CommandWrite(u8 value,int way) {
sio.buf[sio.bufcount-1]=value;
sio.k+=sio.bufcount-5;
}else {
MEMCARDS_LOG("MC(%d) write XOR value error 0x%02X != ^0x%02X\n",
MEMCARDS_LOG("MC(%d) write XOR value error 0x%02X != ^0x%02X",
sio.GetMemcardIndex()+1, value, sio_xor(&sio.buf[3], sio.bufcount-5));
}
}
@ -339,7 +339,7 @@ void SIO_CommandWrite(u8 value,int way) {
//int i;
sio.bufcount=value+5;
sio.buf[3]='+';
MEMCARDS_LOG("MC(%d) READ command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) READ command 0x%02X", sio.GetMemcardIndex()+1, value);
_ReadMcd(&sio.buf[4], (512+16)*sio.sector+sio.k, value);
/*if(sio.mode==2)
{
@ -370,14 +370,14 @@ void SIO_CommandWrite(u8 value,int way) {
sio.buf[2]='+';
sio.buf[3]=sio.terminator;*/
//sio.buf[sio.bufcount] = sio.terminator;
MEMCARDS_LOG("MC(%d) INTERNAL ERASE command 0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) INTERNAL ERASE command 0x%02X", sio.GetMemcardIndex()+1, value);
}
break;
// CARD AUTHENTICATION CHECKS
case 0xF0:
if (sio.parp==2)
{
MEMCARDS_LOG("MC(%d) CARD AUTH :0x%02X\n", sio.GetMemcardIndex()+1, value);
MEMCARDS_LOG("MC(%d) CARD AUTH :0x%02X", sio.GetMemcardIndex()+1, value);
switch(value){
case 1:
case 2:
@ -506,12 +506,12 @@ void InitializeSIO(u8 value)
{
m_PostSavestateCards[mcidx]--;
sio2.packet.recvVal1 = 0x1D100;
PAD_LOG( "START MEMCARD[%d] - post-savestate ejection - reported as missing!\n", sio.GetMemcardIndex() );
PAD_LOG( "START MEMCARD[%d] - post-savestate ejection - reported as missing!", sio.GetMemcardIndex() );
}
else
{
sio2.packet.recvVal1 = MemoryCard::IsPresent( sio.GetMemcardIndex() ) ? 0x1100 : 0x1D100;
PAD_LOG("START MEMCARD [%d] - %s\n",
PAD_LOG("START MEMCARD [%d] - %s",
sio.GetMemcardIndex(), MemoryCard::IsPresent( sio.GetMemcardIndex() ) ? "Present" : "Missing" );
}
@ -543,7 +543,7 @@ void sioWriteCtrl16(u16 value) {
}
void SIO_FORCEINLINE sioInterrupt() {
PAD_LOG("Sio Interrupt\n");
PAD_LOG("Sio Interrupt");
sio.StatReg|= IRQ;
psxHu32(0x1070)|=0x80;
}

2
pcsx2/VU0.cpp
View File

@ -62,7 +62,7 @@ void COP2_SPECIAL2() {
void COP2_Unknown()
{
CPU_LOG("Unknown COP2 opcode called\n");
CPU_LOG("Unknown COP2 opcode called");
}
//****************************************************************************

6
pcsx2/VU0micro.cpp
View File

@ -73,7 +73,7 @@ void VU0MI_XTOP() {
}
void vu0ExecMicro(u32 addr) {
VUM_LOG("vu0ExecMicro %x\n", addr);
VUM_LOG("vu0ExecMicro %x", addr);
if(VU0.VI[REG_VPU_STAT].UL & 0x1) {
DevCon::Notice("vu0ExecMicro > Stalling for previous microprogram to finish");
@ -95,13 +95,13 @@ void vu0ExecMicro(u32 addr) {
void VU0unknown() {
assert(0);
CPU_LOG("Unknown VU micromode opcode called\n");
CPU_LOG("Unknown VU micromode opcode called");
}
void VU0regsunknown(_VURegsNum *VUregsn) {
assert(0);
CPU_LOG("Unknown VU micromode opcode called\n");
CPU_LOG("Unknown VU micromode opcode called");
}
_vuRegsTables(VU0, VU0regs);

8
pcsx2/VU1micro.cpp
View File

@ -77,8 +77,8 @@ void vu1ExecMicro(u32 addr)
CpuVU1.ExecuteBlock();
}
VUM_LOG("vu1ExecMicro %x\n", addr);
VUM_LOG("vu1ExecMicro %x (count=%d)\n", addr, count++);
VUM_LOG("vu1ExecMicro %x", addr);
VUM_LOG("vu1ExecMicro %x (count=%d)", addr, count++);
VU0.VI[REG_VPU_STAT].UL|= 0x100;
VU0.VI[REG_VPU_STAT].UL&= ~0x7E000;
@ -93,12 +93,12 @@ _vuRegsTables(VU1, VU1regs);
void VU1unknown() {
//assert(0);
CPU_LOG("Unknown VU micromode opcode called\n");
CPU_LOG("Unknown VU micromode opcode called");
}
void VU1regsunknown(_VURegsNum *VUregsn) {
//assert(0);
CPU_LOG("Unknown VU micromode opcode called\n");
CPU_LOG("Unknown VU micromode opcode called");
}

4
pcsx2/VU1microInterp.cpp
View File

@ -54,7 +54,7 @@ static void _vu1Exec(VURegs* VU)
int discard=0;
if(VU->VI[REG_TPC].UL >= VU->maxmicro){
CPU_LOG("VU1 memory overflow!!: %x\n", VU->VI[REG_TPC].UL);
CPU_LOG("VU1 memory overflow!!: %x", VU->VI[REG_TPC].UL);
VU->VI[REG_TPC].UL &= 0x3FFF;
/*VU0.VI[REG_VPU_STAT].UL&= ~0x100;
VU->cycle++;
@ -79,7 +79,7 @@ static void _vu1Exec(VURegs* VU)
}
}
VUM_LOG("VU->cycle = %d (flags st=%x;mac=%x;clip=%x,q=%f)\n", VU->cycle, VU->statusflag, VU->macflag, VU->clipflag, VU->q.F);
VUM_LOG("VU->cycle = %d (flags st=%x;mac=%x;clip=%x,q=%f)", VU->cycle, VU->statusflag, VU->macflag, VU->clipflag, VU->q.F);
VU->code = ptr[1];
VU1regs_UPPER_OPCODE[VU->code & 0x3f](&uregs);

6
pcsx2/VUmicro.h
View File

@ -1290,9 +1290,9 @@ void (*PREFIX##_LOWER_OPCODE[128])(_VURegsNum *VUregsn) = { \
#ifdef VUM_LOG
#define IdebugUPPER(VU) \
VUM_LOG("%s\n", dis##VU##MicroUF(VU.code, VU.VI[REG_TPC].UL));
VUM_LOG("%s", dis##VU##MicroUF(VU.code, VU.VI[REG_TPC].UL));
#define IdebugLOWER(VU) \
VUM_LOG("%s\n", dis##VU##MicroLF(VU.code, VU.VI[REG_TPC].UL));
VUM_LOG("%s", dis##VU##MicroLF(VU.code, VU.VI[REG_TPC].UL));
#else
@ -1303,7 +1303,7 @@ void (*PREFIX##_LOWER_OPCODE[128])(_VURegsNum *VUregsn) = { \
#ifdef VUM_LOG
#define _vuExecMicroDebug(VU) \
VUM_LOG("_vuExecMicro: %8.8x\n", VU.VI[REG_TPC].UL);
VUM_LOG("_vuExecMicro: %8.8x", VU.VI[REG_TPC].UL);
#else
#define _vuExecMicroDebug(VU)
#endif

22
pcsx2/VUops.cpp
View File

@ -54,7 +54,7 @@ void _vuFMACflush(VURegs * VU) {
if (VU->fmac[i].enable == 0) continue;
if ((VU->cycle - VU->fmac[i].sCycle) >= VU->fmac[i].Cycle) {
VUM_LOG("flushing FMAC pipe[%d] (macflag=%x)\n", i, VU->fmac[i].macflag);
VUM_LOG("flushing FMAC pipe[%d] (macflag=%x)", i, VU->fmac[i].macflag);
VU->fmac[i].enable = 0;
VU->VI[REG_MAC_FLAG].UL = VU->fmac[i].macflag;
@ -68,7 +68,7 @@ void _vuFDIVflush(VURegs * VU) {
if (VU->fdiv.enable == 0) return;
if ((VU->cycle - VU->fdiv.sCycle) >= VU->fdiv.Cycle) {
VUM_LOG("flushing FDIV pipe\n");
VUM_LOG("flushing FDIV pipe");
VU->fdiv.enable = 0;
VU->VI[REG_Q].UL = VU->fdiv.reg.UL;
@ -80,7 +80,7 @@ void _vuEFUflush(VURegs * VU) {
if (VU->efu.enable == 0) return;
if ((VU->cycle - VU->efu.sCycle) >= VU->efu.Cycle) {
// VUM_LOG("flushing EFU pipe\n");
// VUM_LOG("flushing EFU pipe");
VU->efu.enable = 0;
VU->VI[REG_P].UL = VU->efu.reg.UL;
@ -101,7 +101,7 @@ void _vuFlushAll(VURegs* VU)
nRepeat = 1;
if ((VU->cycle - VU->fmac[i].sCycle) >= VU->fmac[i].Cycle) {
VUM_LOG("flushing FMAC pipe[%d] (macflag=%x)\n", i, VU->fmac[i].macflag);
VUM_LOG("flushing FMAC pipe[%d] (macflag=%x)", i, VU->fmac[i].macflag);
VU->fmac[i].enable = 0;
VU->VI[REG_MAC_FLAG].UL = VU->fmac[i].macflag;
@ -115,7 +115,7 @@ void _vuFlushAll(VURegs* VU)
nRepeat = 1;
if ((VU->cycle - VU->fdiv.sCycle) >= VU->fdiv.Cycle) {
VUM_LOG("flushing FDIV pipe\n");
VUM_LOG("flushing FDIV pipe");
nRepeat = 1;
VU->fdiv.enable = 0;
@ -129,7 +129,7 @@ void _vuFlushAll(VURegs* VU)
nRepeat = 1;
if ((VU->cycle - VU->efu.sCycle) >= VU->efu.Cycle) {
// VUM_LOG("flushing EFU pipe\n");
// VUM_LOG("flushing EFU pipe");
nRepeat = 1;
VU->efu.enable = 0;
@ -165,7 +165,7 @@ void _vuFMACTestStall(VURegs * VU, int reg, int xyzw) {
VU->VI[REG_MAC_FLAG].UL = VU->fmac[i].macflag;
VU->VI[REG_STATUS_FLAG].UL = VU->fmac[i].statusflag;
VU->VI[REG_CLIP_FLAG].UL = VU->fmac[i].clipflag;
VUM_LOG("FMAC[%d] stall %d\n", i, cycle);
VUM_LOG("FMAC[%d] stall %d", i, cycle);
VU->cycle+= cycle;
_vuTestPipes(VU);
@ -182,7 +182,7 @@ void _vuFMACAdd(VURegs * VU, int reg, int xyzw) {
//if (i==8) Console::Error("*PCSX2*: error , out of fmacs %d", params VU->cycle);
VUM_LOG("adding FMAC pipe[%d]; xyzw=%x\n", i, xyzw);
VUM_LOG("adding FMAC pipe[%d]; xyzw=%x", i, xyzw);
VU->fmac[i].enable = 1;
VU->fmac[i].sCycle = VU->cycle;
@ -195,7 +195,7 @@ void _vuFMACAdd(VURegs * VU, int reg, int xyzw) {
}
void _vuFDIVAdd(VURegs * VU, int cycles) {
VUM_LOG("adding FDIV pipe\n");
VUM_LOG("adding FDIV pipe");
VU->fdiv.enable = 1;
VU->fdiv.sCycle = VU->cycle;
@ -219,7 +219,7 @@ void _vuFlushFDIV(VURegs * VU) {
if (VU->fdiv.enable == 0) return;
cycle = VU->fdiv.Cycle - (VU->cycle - VU->fdiv.sCycle);
VUM_LOG("waiting FDIV pipe %d\n", cycle);
VUM_LOG("waiting FDIV pipe %d", cycle);
VU->fdiv.enable = 0;
VU->cycle+= cycle;
@ -233,7 +233,7 @@ void _vuFlushEFU(VURegs * VU) {
if (VU->efu.enable == 0) return;
cycle = VU->efu.Cycle - (VU->cycle - VU->efu.sCycle);
// VUM_LOG("waiting EFU pipe %d\n", cycle);
// VUM_LOG("waiting EFU pipe %d", cycle);
VU->efu.enable = 0;
VU->cycle+= cycle;

28
pcsx2/Vif.cpp
View File

@ -93,7 +93,7 @@ static __releaseinline void writeX( u32 *dest, u32 data ) {
}
break;
}
// VIF_LOG("writeX %8.8x : Mode %d, r0 = %x, data %8.8x\n", *dest,_vifRegs->mode,_vifRegs->r0,data);
// VIF_LOG("writeX %8.8x : Mode %d, r0 = %x, data %8.8x", *dest,_vifRegs->mode,_vifRegs->r0,data);
}
static __releaseinline void writeY( u32 *dest, u32 data ) {
@ -132,7 +132,7 @@ static __releaseinline void writeY( u32 *dest, u32 data ) {
}
break;
}
// VIF_LOG("writeY %8.8x : Mode %d, r1 = %x, data %8.8x\n", *dest,_vifRegs->mode,_vifRegs->r1,data);
// VIF_LOG("writeY %8.8x : Mode %d, r1 = %x, data %8.8x", *dest,_vifRegs->mode,_vifRegs->r1,data);
}
static __releaseinline void writeZ( u32 *dest, u32 data ) {
@ -171,7 +171,7 @@ static __releaseinline void writeZ( u32 *dest, u32 data ) {
}
break;
}
// VIF_LOG("writeZ %8.8x : Mode %d, r2 = %x, data %8.8x\n", *dest,_vifRegs->mode,_vifRegs->r2,data);
// VIF_LOG("writeZ %8.8x : Mode %d, r2 = %x, data %8.8x", *dest,_vifRegs->mode,_vifRegs->r2,data);
}
static __releaseinline void writeW( u32 *dest, u32 data ) {
@ -210,7 +210,7 @@ static __releaseinline void writeW( u32 *dest, u32 data ) {
}
break;
}
// VIF_LOG("writeW %8.8x : Mode %d, r3 = %x, data %8.8x\n", *dest,_vifRegs->mode,_vifRegs->r3,data);
// VIF_LOG("writeW %8.8x : Mode %d, r3 = %x, data %8.8x", *dest,_vifRegs->mode,_vifRegs->r3,data);
}
void __fastcall UNPACK_S_32(u32 *dest, u32 *data, int size) {
@ -412,7 +412,7 @@ static __forceinline int mfifoVIF1rbTransfer() {
if ((vif1ch->madr+(mfifoqwc << 4)) > (msize)) {
int s1 = ((msize) - vif1ch->madr) >> 2;
SPR_LOG("Split MFIFO\n");
SPR_LOG("Split MFIFO");
/* it does, so first copy 's1' bytes from 'addr' to 'data' */
src = (u32*)PSM(vif1ch->madr);
@ -432,7 +432,7 @@ static __forceinline int mfifoVIF1rbTransfer() {
ret = VIF1transfer(src, ((mfifoqwc << 2) - s1), 0);
} else
{
SPR_LOG("Direct MFIFO\n");
SPR_LOG("Direct MFIFO");
/* it doesn't, so just transfer 'qwc*4' words */
src = (u32*)PSM(vif1ch->madr);
@ -465,7 +465,7 @@ static __forceinline int mfifoVIF1chain() {
vifqwc -= startqwc - vif1ch->qwc;
} else {
u32 *pMem = (u32*)dmaGetAddr(vif1ch->madr);
SPR_LOG("Non-MFIFO Location\n");
SPR_LOG("Non-MFIFO Location");
if (pMem == NULL) return -1;
if(vif1.vifstalled == 1){
@ -504,7 +504,7 @@ void mfifoVIF1transfer(int qwc) {
}
}
vif1.inprogress &= ~0x10;
SPR_LOG("Added %x qw to mfifo, total now %x - Vif CHCR %x Stalled %x done %x\n", qwc, vifqwc, vif1ch->chcr, vif1.vifstalled, vif1.done);
SPR_LOG("Added %x qw to mfifo, total now %x - Vif CHCR %x Stalled %x done %x", qwc, vifqwc, vif1ch->chcr, vif1.vifstalled, vif1.done);
/*if((vif1ch->chcr & 0x100) == 0 || vif1.vifstalled == 1 || vif1.done == 1 || vif1.inprogress == 1)*/ return;
}
@ -519,7 +519,7 @@ void mfifoVIF1transfer(int qwc) {
if( vif1.stallontag == 1) ret = VIF1transfer(ptag+(2+vif1.irqoffset), 2-vif1.irqoffset, 1); //Transfer Tag on Stall
else ret = VIF1transfer(ptag+2, 2, 1); //Transfer Tag
if (ret == -2) {
VIF_LOG("MFIFO Stallon tag\n");
VIF_LOG("MFIFO Stallon tag");
vif1.stallontag = 1;
//CPU_INT(10,cycles+g_vifCycles);
@ -534,7 +534,7 @@ void mfifoVIF1transfer(int qwc) {
vif1ch->chcr = ( vif1ch->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 );
SPR_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx mfifo qwc = %x spr0 madr = %x\n",
SPR_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx mfifo qwc = %x spr0 madr = %x",
ptag[1], ptag[0], vif1ch->qwc, id, vif1ch->madr, vif1ch->tadr, vifqwc, spr0->madr);
vifqwc--;
@ -573,7 +573,7 @@ void mfifoVIF1transfer(int qwc) {
if ((vif1ch->chcr & 0x80) && (ptag[0] >> 31))
{
VIF_LOG("dmaIrq Set\n");
VIF_LOG("dmaIrq Set");
vif1.done = 1;
mfifodmairq = 1; //Let the handler know we have prematurely ended MFIFO
}
@ -587,14 +587,14 @@ void mfifoVIF1transfer(int qwc) {
//CPU_INT(10,g_vifCycles);
}
if(ret == -2){
VIF_LOG("MFIFO Stall\n");
VIF_LOG("MFIFO Stall");
//CPU_INT(10,g_vifCycles);
return;
}*/
//if(vif1.done == 2 && vif1ch->qwc == 0) vif1.done = 1;
//CPU_INT(10,g_vifCycles);
SPR_LOG("mfifoVIF1transfer end %x madr %x, tadr %x vifqwc %x\n", vif1ch->chcr, vif1ch->madr, vif1ch->tadr, vifqwc);
SPR_LOG("mfifoVIF1transfer end %x madr %x, tadr %x vifqwc %x", vif1ch->chcr, vif1ch->madr, vif1ch->tadr, vifqwc);
}
void vifMFIFOInterrupt()
@ -655,7 +655,7 @@ void vifMFIFOInterrupt()
g_vifCycles = 0;
vif1ch->chcr &= ~0x100;
hwDmacIrq(DMAC_VIF1);
VIF_LOG("vif mfifo dma end\n");
VIF_LOG("vif mfifo dma end");
vif1Regs->stat&= ~0x1F000000; // FQC=0

108
pcsx2/VifDma.cpp
View File

@ -254,55 +254,55 @@ static void ProcessMemSkip(int size, unsigned int unpackType, const unsigned int
switch(unpackType){
case 0x0:
vif->tag.addr += size*4;
VIFUNPACK_LOG("Processing S-32 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing S-32 skip, size = %d", size);
break;
case 0x1:
vif->tag.addr += size*8;
VIFUNPACK_LOG("Processing S-16 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing S-16 skip, size = %d", size);
break;
case 0x2:
vif->tag.addr += size*16;
VIFUNPACK_LOG("Processing S-8 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing S-8 skip, size = %d", size);
break;
case 0x4:
vif->tag.addr += size + ((size / unpack->gsize) * 8);
VIFUNPACK_LOG("Processing V2-32 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V2-32 skip, size = %d", size);
break;
case 0x5:
vif->tag.addr += (size * 2) + ((size / unpack->gsize) * 8);
VIFUNPACK_LOG("Processing V2-16 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V2-16 skip, size = %d", size);
break;
case 0x6:
vif->tag.addr += (size * 4) + ((size / unpack->gsize) * 8);
VIFUNPACK_LOG("Processing V2-8 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V2-8 skip, size = %d", size);
break;
case 0x8:
vif->tag.addr += size + ((size / unpack->gsize) * 4);
VIFUNPACK_LOG("Processing V3-32 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V3-32 skip, size = %d", size);
break;
case 0x9:
vif->tag.addr += (size * 2) + ((size / unpack->gsize) * 4);
VIFUNPACK_LOG("Processing V3-16 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V3-16 skip, size = %d", size);
break;
case 0xA:
vif->tag.addr += (size * 4) + ((size / unpack->gsize) * 4);
VIFUNPACK_LOG("Processing V3-8 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V3-8 skip, size = %d", size);
break;
case 0xC:
vif->tag.addr += size;
VIFUNPACK_LOG("Processing V4-32 skip, size = %d, CL = %d, WL = %d\n", size, vif1Regs->cycle.cl, vif1Regs->cycle.wl);
VIFUNPACK_LOG("Processing V4-32 skip, size = %d, CL = %d, WL = %d", size, vif1Regs->cycle.cl, vif1Regs->cycle.wl);
break;
case 0xD:
vif->tag.addr += size * 2;
VIFUNPACK_LOG("Processing V4-16 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V4-16 skip, size = %d", size);
break;
case 0xE:
vif->tag.addr += size * 4;
VIFUNPACK_LOG("Processing V4-8 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V4-8 skip, size = %d", size);
break;
case 0xF:
vif->tag.addr += size * 8;
VIFUNPACK_LOG("Processing V4-5 skip, size = %d\n", size);
VIFUNPACK_LOG("Processing V4-5 skip, size = %d", size);
break;
default:
Console::WriteLn("Invalid unpack type %x", params unpackType);
@ -361,16 +361,16 @@ static void VIFunpack(u32 *data, vifCode *v, int size, const unsigned int VIFdma
dest = (u32*)(VU->Mem + v->addr);
VIF_LOG("VIF%d UNPACK: Mode=%x, v->size=%d, size=%d, v->addr=%x\n",
VIF_LOG("VIF%d UNPACK: Mode=%x, v->size=%d, size=%d, v->addr=%x",
VIFdmanum, v->cmd & 0xf, v->size, size, v->addr );
#ifdef _DEBUG
if (v->size != size) {
VIF_LOG("*PCSX2*: warning v->size != size\n");
VIF_LOG("*PCSX2*: warning v->size != size");
}
if ((v->addr+size*4) > memsize) {
Console::Notice("*PCSX2*: fixme unpack overflow\n");
Console::WriteLn( "VIF%d UNPACK: Mode=%x, v->size=%d, size=%d, v->addr=%x\n",
Console::Notice("*PCSX2*: fixme unpack overflow");
Console::WriteLn( "VIF%d UNPACK: Mode=%x, v->size=%d, size=%d, v->addr=%x",
params VIFdmanum, v->cmd & 0xf, v->size, size, v->addr );
}
#endif
@ -378,7 +378,7 @@ static void VIFunpack(u32 *data, vifCode *v, int size, const unsigned int VIFdma
unpackType = v->cmd & 0xf;
if (size == 0) {
VIFUNPACK_LOG("*PCSX2*: Unpack %x with size 0!! v->size = %d cl = %d, wl = %d, mode %d mask %x\n", v->cmd, v->size, vifRegs->cycle.cl, vifRegs->cycle.wl, vifRegs->mode, vifRegs->mask);
VIFUNPACK_LOG("*PCSX2*: Unpack %x with size 0!! v->size = %d cl = %d, wl = %d, mode %d mask %x", v->cmd, v->size, vifRegs->cycle.cl, vifRegs->cycle.wl, vifRegs->mode, vifRegs->mask);
}
//#ifdef _MSC_VER
@ -399,7 +399,7 @@ static void VIFunpack(u32 *data, vifCode *v, int size, const unsigned int VIFdma
{
int destinc, unpacksize;
VIFUNPACK_LOG("aligning packet size = %d offset %d addr %x\n", size, vifRegs->offset, vif->tag.addr);
VIFUNPACK_LOG("aligning packet size = %d offset %d addr %x", size, vifRegs->offset, vif->tag.addr);
// SSE doesn't handle such small data
if (v->size != (size>>2))
@ -437,7 +437,7 @@ static void VIFunpack(u32 *data, vifCode *v, int size, const unsigned int VIFdma
else {
dest += destinc;
}
VIFUNPACK_LOG("aligning packet done size = %d offset %d addr %x\n", size, vifRegs->offset, vif->tag.addr);
VIFUNPACK_LOG("aligning packet done size = %d offset %d addr %x", size, vifRegs->offset, vif->tag.addr);
}
else if (v->size != (size>>2))
@ -616,20 +616,20 @@ static void VIFunpack(u32 *data, vifCode *v, int size, const unsigned int VIFdma
// s_count++;
if( size >= ft->dsize && vifRegs->num > 0) {
//VIF_LOG("warning, end with size = %d\n", size);
//VIF_LOG("warning, end with size = %d", size);
/* unpack one qword */
func(dest, (u32*)cdata, size / ft->dsize);
size = 0;
VIFUNPACK_LOG("leftover done, size %d, vifnum %d, addr %x\n", size, vifRegs->num, vif->tag.addr);
VIFUNPACK_LOG("leftover done, size %d, vifnum %d, addr %x", size, vifRegs->num, vif->tag.addr);
}
}
else { /* filling write */
VIF_LOG("VIFunpack - filling write\n");
VIF_LOG("VIFunpack - filling write");
VIFUNPACK_LOG("filling write %d cl %d, wl %d mask %x mode %x unpacktype %x\n", vifRegs->num, vifRegs->cycle.cl, vifRegs->cycle.wl, vifRegs->mask, vifRegs->mode, unpackType);
VIFUNPACK_LOG("filling write %d cl %d, wl %d mask %x mode %x unpacktype %x", vifRegs->num, vifRegs->cycle.cl, vifRegs->cycle.wl, vifRegs->mask, vifRegs->mode, unpackType);
while (size >= ft->gsize || vifRegs->num > 0) {
if (vif->cl == vifRegs->cycle.wl) {
vif->cl = 0;
@ -784,7 +784,7 @@ static int __fastcall Vif0TransNull(u32 *data){ // Shouldnt go here
static int __fastcall Vif0TransSTMask(u32 *data){ // STMASK
SetNewMask(g_vif0Masks, g_vif0HasMask3, data[0], vif0Regs->mask);
vif0Regs->mask = data[0];
VIF_LOG("STMASK == %x\n", vif0Regs->mask);
VIF_LOG("STMASK == %x", vif0Regs->mask);
vif0.tag.size = 0;
vif0.cmd = 0;
@ -951,7 +951,7 @@ static void Vif0CMDNull(){ // invalid opcode
int VIF0transfer(u32 *data, int size, int istag) {
int ret;
int transferred=vif0.vifstalled ? vif0.irqoffset : 0; // irqoffset necessary to add up the right qws, or else will spin (spiderman)
VIF_LOG( "VIF0transfer: size %x (vif0.cmd %x)\n", size, vif0.cmd );
VIF_LOG( "VIF0transfer: size %x (vif0.cmd %x)", size, vif0.cmd );
vif0.stallontag = 0;
vif0.vifstalled = 0;
@ -984,7 +984,7 @@ int VIF0transfer(u32 *data, int size, int istag) {
if ((vif0.cmd & 0x60) == 0x60) {
vif0UNPACK(data);
} else {
VIF_LOG( "VIFtransfer: cmd %x, num %x, imm %x, size %x\n", vif0.cmd, (data[0] >> 16) & 0xff, data[0] & 0xffff, size );
VIF_LOG( "VIFtransfer: cmd %x, num %x, imm %x, size %x", vif0.cmd, (data[0] >> 16) & 0xff, data[0] & 0xffff, size );
if((vif0.cmd & 0x7f) > 0x4A){
if ((vif0Regs->err & 0x4) == 0) { //Ignore vifcode and tag mismatch error
@ -1004,7 +1004,7 @@ int VIF0transfer(u32 *data, int size, int istag) {
if(!(vif0Regs->err & 0x1)) //i bit on vifcode and not masked by VIF0_ERR
{
VIF_LOG( "Interrupt on VIFcmd: %x (INTC_MASK = %x)\n", vif0.cmd, psHu32(INTC_MASK) );
VIF_LOG( "Interrupt on VIFcmd: %x (INTC_MASK = %x)", vif0.cmd, psHu32(INTC_MASK) );
++vif0.irq;
@ -1062,12 +1062,10 @@ int _VIF0chain() {
if (pMem == NULL)
return -1;
if( vif0.vifstalled ) {
if( vif0.vifstalled )
ret = VIF0transfer(pMem+vif0.irqoffset, vif0ch->qwc*4-vif0.irqoffset, 0);
}
else {
else
ret = VIF0transfer(pMem, vif0ch->qwc*4, 0);
}
return ret;
}
@ -1091,7 +1089,7 @@ int _chainVIF0() {
vif0ch->qwc = (u16)vif0ptag[0]; //QWC set to lower 16bits of the tag
vif0ch->madr = vif0ptag[1]; //MADR = ADDR field
g_vifCycles+=1; // Add 1 g_vifCycles from the QW read for the tag
VIF_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx\n",
VIF_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx",
vif0ptag[1], vif0ptag[0], vif0ch->qwc, id, vif0ch->madr, vif0ch->tadr);
vif0ch->chcr = ( vif0ch->chcr & 0xFFFF ) | ( (*vif0ptag) & 0xFFFF0000 ); //Transfer upper part of tag to CHCR bits 31-15
@ -1101,14 +1099,12 @@ int _chainVIF0() {
if(vif0.vifstalled == 1) ret = VIF0transfer(vif0ptag+(2+vif0.irqoffset), 2-vif0.irqoffset, 1); //Transfer Tag on stall
else ret = VIF0transfer(vif0ptag+2, 2, 1); //Transfer Tag
if (ret == -1) return -1; //There has been an error
if (ret == -2) {
return -2; //IRQ set by VIFTransfer
}
if (ret == -2) return -2; //IRQ set by VIFTransfer
}
vif0.done |= hwDmacSrcChainWithStack(vif0ch, id);
VIF_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx\n",
VIF_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx",
vif0ptag[1], vif0ptag[0], vif0ch->qwc, id, vif0ch->madr, vif0ch->tadr);
@ -1127,7 +1123,7 @@ int _chainVIF0() {
void vif0Interrupt() {
// int ret;
g_vifCycles = 0; //Reset the cycle count, Wouldnt reset on stall if put lower down.
VIF_LOG("vif0Interrupt: %8.8x\n", cpuRegs.cycle);
VIF_LOG("vif0Interrupt: %8.8x", cpuRegs.cycle);
if(vif0.irq && vif0.tag.size == 0) {
@ -1158,7 +1154,7 @@ void vif0Interrupt() {
if (vif0ch->chcr & 0x4 && vif0.done == 0 && vif0.vifstalled == 0) {
if( !(psHu32(DMAC_CTRL) & 0x1) ) {
Console::WriteLn("vif0 dma masked\n");
Console::WriteLn("vif0 dma masked");
return;
}
@ -1244,7 +1240,7 @@ void dmaVIF0() {
void vif0Write32(u32 mem, u32 value) {
if (mem == 0x10003830) // MARK
{
VIF_LOG("VIF0_MARK write32 0x%8.8x\n", value);
VIF_LOG("VIF0_MARK write32 0x%8.8x", value);
/* Clear mark flag in VIF0_STAT and set mark with 'value' */
vif0Regs->stat&= ~VIF0_STAT_MRK;
@ -1252,7 +1248,7 @@ void vif0Write32(u32 mem, u32 value) {
}
else if (mem == 0x10003810) // FBRST
{
VIF_LOG("VIF0_FBRST write32 0x%8.8x\n", value);
VIF_LOG("VIF0_FBRST write32 0x%8.8x", value);
if (value & 0x1)
{
@ -1319,7 +1315,7 @@ void vif0Write32(u32 mem, u32 value) {
}
else if (mem == 0x10003820)
{ // ERR
VIF_LOG("VIF0_ERR write32 0x%8.8x\n", value);
VIF_LOG("VIF0_ERR write32 0x%8.8x", value);
/* Set VIF0_ERR with 'value' */
vif0Regs->err = value;
@ -1458,7 +1454,7 @@ static int __fastcall Vif1TransNull(u32 *data){ // Shouldnt go here
static int __fastcall Vif1TransSTMask(u32 *data){ // STMASK
SetNewMask(g_vif1Masks, g_vif1HasMask3, data[0], vif1Regs->mask);
vif1Regs->mask = data[0];
VIF_LOG("STMASK == %x\n", vif1Regs->mask);
VIF_LOG("STMASK == %x", vif1Regs->mask);
vif1.tag.size = 0;
vif1.cmd = 0;
@ -1820,7 +1816,7 @@ int VIF1transfer(u32 *data, int size, int istag) {
int ret;
transferred=vif1.vifstalled ? vif1.irqoffset : 0; // irqoffset necessary to add up the right qws, or else will spin (spiderman)
VIF_LOG( "VIF1transfer: size %x (vif1.cmd %x)\n", size, vif1.cmd );
VIF_LOG( "VIF1transfer: size %x (vif1.cmd %x)", size, vif1.cmd );
vif1.irqoffset = 0;
vif1.vifstalled = 0;
@ -1840,7 +1836,7 @@ int VIF1transfer(u32 *data, int size, int istag) {
continue;
}
if(vif1.tag.size != 0) DevCon::Error("no vif1 cmd but tag size is left last cmd read %x\n", params vif1Regs->code);
if(vif1.tag.size != 0) DevCon::Error("no vif1 cmd but tag size is left last cmd read %x", params vif1Regs->code);
if(vif1.irq) break;
@ -1853,11 +1849,11 @@ int VIF1transfer(u32 *data, int size, int istag) {
}
else
{
VIF_LOG( "VIFtransfer: cmd %x, num %x, imm %x, size %x\n", vif1.cmd, (data[0] >> 16) & 0xff, data[0] & 0xffff, vif1.vifpacketsize );
VIF_LOG( "VIFtransfer: cmd %x, num %x, imm %x, size %x", vif1.cmd, (data[0] >> 16) & 0xff, data[0] & 0xffff, vif1.vifpacketsize );
if((vif1.cmd & 0x7f) > 0x51){
if ((vif1Regs->err & 0x4) == 0) { //Ignore vifcode and tag mismatch error
Console::WriteLn( "UNKNOWN VifCmd: %x\n", params vif1.cmd );
Console::WriteLn( "UNKNOWN VifCmd: %x", params vif1.cmd );
vif1Regs->stat |= 1 << 13;
vif1.irq++;
}
@ -1875,7 +1871,7 @@ int VIF1transfer(u32 *data, int size, int istag) {
if(!(vif1Regs->err & 0x1)) //i bit on vifcode and not masked by VIF1_ERR
{
VIF_LOG( "Interrupt on VIFcmd: %x (INTC_MASK = %x)\n", vif1.cmd, psHu32(INTC_MASK) );
VIF_LOG( "Interrupt on VIFcmd: %x (INTC_MASK = %x)", vif1.cmd, psHu32(INTC_MASK) );
++vif1.irq;
@ -1991,7 +1987,7 @@ int _VIF1chain() {
if (pMem == NULL)
return -1;
VIF_LOG("VIF1chain size=%d, madr=%lx, tadr=%lx\n",
VIF_LOG("VIF1chain size=%d, madr=%lx, tadr=%lx",
vif1ch->qwc, vif1ch->madr, vif1ch->tadr);
if( vif1.vifstalled )
@ -2072,7 +2068,7 @@ __forceinline void vif1SetupTransfer() {
vif1.done |= hwDmacSrcChainWithStack(vif1ch, id);
if ((vif1ch->chcr & 0x80) && (vif1ptag[0] >> 31)) { //Check TIE bit of CHCR and IRQ bit of tag
VIF_LOG( "dmaIrq Set\n" );
VIF_LOG( "dmaIrq Set" );
vif1.done = 1;
return; //End Transfer
@ -2081,7 +2077,7 @@ __forceinline void vif1SetupTransfer() {
}
}
__forceinline void vif1Interrupt() {
VIF_LOG("vif1Interrupt: %8.8x\n", cpuRegs.cycle);
VIF_LOG("vif1Interrupt: %8.8x", cpuRegs.cycle);
g_vifCycles = 0;
@ -2142,7 +2138,7 @@ void dmaVIF1()
{
VIF_LOG("dmaVIF1 chcr = %lx, madr = %lx, qwc = %lx\n"
" tadr = %lx, asr0 = %lx, asr1 = %lx\n",
" tadr = %lx, asr0 = %lx, asr1 = %lx",
vif1ch->chcr, vif1ch->madr, vif1ch->qwc,
vif1ch->tadr, vif1ch->asr0, vif1ch->asr1 );
@ -2245,14 +2241,14 @@ void dmaVIF1()
void vif1Write32(u32 mem, u32 value) {
if (mem == 0x10003c30) { // MARK
VIF_LOG("VIF1_MARK write32 0x%8.8x\n", value);
VIF_LOG("VIF1_MARK write32 0x%8.8x", value);
/* Clear mark flag in VIF1_STAT and set mark with 'value' */
vif1Regs->stat&= ~VIF1_STAT_MRK;
vif1Regs->mark = value;
}
else if (mem == 0x10003c10) { // FBRST
VIF_LOG("VIF1_FBRST write32 0x%8.8x\n", value);
VIF_LOG("VIF1_FBRST write32 0x%8.8x", value);
if (value & 0x1) {
/* Reset VIF */
@ -2322,13 +2318,13 @@ void vif1Write32(u32 mem, u32 value) {
}
}
else if (mem == 0x10003c20) { // ERR
VIF_LOG("VIF1_ERR write32 0x%8.8x\n", value);
VIF_LOG("VIF1_ERR write32 0x%8.8x", value);
/* Set VIF1_ERR with 'value' */
vif1Regs->err = value;
}
else if (mem == 0x10003c00) { // STAT
VIF_LOG("VIF1_STAT write32 0x%8.8x\n", value);
VIF_LOG("VIF1_STAT write32 0x%8.8x", value);
#ifdef PCSX2_DEVBUILD
/* Only FDR bit is writable, so mask the rest */

4
pcsx2/configure.ac
View File

@ -1,5 +1,5 @@
AC_INIT(pcsx2,0.9.5,zerofrog@gmail.com)
AM_INIT_AUTOMAKE(pcsx2,0.9.5)
AC_INIT(pcsx2,0.9.6,zerofrog@gmail.com)
AM_INIT_AUTOMAKE(pcsx2,0.9.6)
AC_PROG_CC([gcc g++ cl KCC CC cxx cc++ xlC aCC c++])
AC_PROG_CXX([gcc g++ cl KCC CC cxx cc++ xlC aCC c++])

44
pcsx2/x86/iCore.cpp
View File

@ -1167,39 +1167,39 @@ void iDumpRegisters(u32 startpc, u32 temp)
psymb = disR5900GetSym(startpc);
if( psymb != NULL )
__Log("%sreg(%s): %x %x c:%x\n", pstr, psymb, startpc, cpuRegs.interrupt, cpuRegs.cycle);
__Log("%sreg(%s): %x %x c:%x", pstr, psymb, startpc, cpuRegs.interrupt, cpuRegs.cycle);
else
__Log("%sreg: %x %x c:%x\n", pstr, startpc, cpuRegs.interrupt, cpuRegs.cycle);
for(i = 1; i < 32; ++i) __Log("%s: %x_%x_%x_%x\n", disRNameGPR[i], cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0]);
//for(i = 0; i < 32; i+=4) __Log("cp%d: %x_%x_%x_%x\n", i, cpuRegs.CP0.r[i], cpuRegs.CP0.r[i+1], cpuRegs.CP0.r[i+2], cpuRegs.CP0.r[i+3]);
//for(i = 0; i < 32; ++i) __Log("%sf%d: %f %x\n", pstr, i, fpuRegs.fpr[i].f, fpuRegs.fprc[i]);
//for(i = 1; i < 32; ++i) __Log("%svf%d: %f %f %f %f, vi: %x\n", pstr, i, VU0.VF[i].F[3], VU0.VF[i].F[2], VU0.VF[i].F[1], VU0.VF[i].F[0], VU0.VI[i].UL);
for(i = 0; i < 32; ++i) __Log("%sf%d: %x %x\n", pstr, i, fpuRegs.fpr[i].UL, fpuRegs.fprc[i]);
for(i = 1; i < 32; ++i) __Log("%svf%d: %x %x %x %x, vi: %x\n", pstr, i, VU0.VF[i].UL[3], VU0.VF[i].UL[2], VU0.VF[i].UL[1], VU0.VF[i].UL[0], VU0.VI[i].UL);
__Log("%svfACC: %x %x %x %x\n", pstr, VU0.ACC.UL[3], VU0.ACC.UL[2], VU0.ACC.UL[1], VU0.ACC.UL[0]);
__Log("%sLO: %x_%x_%x_%x, HI: %x_%x_%x_%x\n", pstr, cpuRegs.LO.UL[3], cpuRegs.LO.UL[2], cpuRegs.LO.UL[1], cpuRegs.LO.UL[0],
__Log("%sreg: %x %x c:%x", pstr, startpc, cpuRegs.interrupt, cpuRegs.cycle);
for(i = 1; i < 32; ++i) __Log("%s: %x_%x_%x_%x", disRNameGPR[i], cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0]);
//for(i = 0; i < 32; i+=4) __Log("cp%d: %x_%x_%x_%x", i, cpuRegs.CP0.r[i], cpuRegs.CP0.r[i+1], cpuRegs.CP0.r[i+2], cpuRegs.CP0.r[i+3]);
//for(i = 0; i < 32; ++i) __Log("%sf%d: %f %x", pstr, i, fpuRegs.fpr[i].f, fpuRegs.fprc[i]);
//for(i = 1; i < 32; ++i) __Log("%svf%d: %f %f %f %f, vi: %x", pstr, i, VU0.VF[i].F[3], VU0.VF[i].F[2], VU0.VF[i].F[1], VU0.VF[i].F[0], VU0.VI[i].UL);
for(i = 0; i < 32; ++i) __Log("%sf%d: %x %x", pstr, i, fpuRegs.fpr[i].UL, fpuRegs.fprc[i]);
for(i = 1; i < 32; ++i) __Log("%svf%d: %x %x %x %x, vi: %x", pstr, i, VU0.VF[i].UL[3], VU0.VF[i].UL[2], VU0.VF[i].UL[1], VU0.VF[i].UL[0], VU0.VI[i].UL);
__Log("%svfACC: %x %x %x %x", pstr, VU0.ACC.UL[3], VU0.ACC.UL[2], VU0.ACC.UL[1], VU0.ACC.UL[0]);
__Log("%sLO: %x_%x_%x_%x, HI: %x_%x_%x_%x", pstr, cpuRegs.LO.UL[3], cpuRegs.LO.UL[2], cpuRegs.LO.UL[1], cpuRegs.LO.UL[0],
cpuRegs.HI.UL[3], cpuRegs.HI.UL[2], cpuRegs.HI.UL[1], cpuRegs.HI.UL[0]);
__Log("%sCycle: %x %x, Count: %x\n", pstr, cpuRegs.cycle, g_nextBranchCycle, cpuRegs.CP0.n.Count);
__Log("%sCycle: %x %x, Count: %x", pstr, cpuRegs.cycle, g_nextBranchCycle, cpuRegs.CP0.n.Count);
iDumpPsxRegisters(psxRegs.pc, temp);
__Log("f410,30,40: %x %x %x, %d %d\n", psHu32(0xf410), psHu32(0xf430), psHu32(0xf440), rdram_sdevid, rdram_devices);
__Log("cyc11: %x %x; vu0: %x, vu1: %x\n", cpuRegs.sCycle[1], cpuRegs.eCycle[1], VU0.cycle, VU1.cycle);
__Log("f410,30,40: %x %x %x, %d %d", psHu32(0xf410), psHu32(0xf430), psHu32(0xf440), rdram_sdevid, rdram_devices);
__Log("cyc11: %x %x; vu0: %x, vu1: %x", cpuRegs.sCycle[1], cpuRegs.eCycle[1], VU0.cycle, VU1.cycle);
__Log("%scounters: %x %x; psx: %x %x\n", pstr, nextsCounter, nextCounter, psxNextsCounter, psxNextCounter);
__Log("%scounters: %x %x; psx: %x %x", pstr, nextsCounter, nextCounter, psxNextsCounter, psxNextCounter);
for(i = 0; i < 4; ++i) {
__Log("eetimer%d: count: %x mode: %x target: %x %x; %x %x; %x %x %x %x\n", i,
__Log("eetimer%d: count: %x mode: %x target: %x %x; %x %x; %x %x %x %x", i,
counters[i].count, counters[i].mode, counters[i].target, counters[i].hold, counters[i].rate,
counters[i].interrupt, counters[i].Cycle, counters[i].sCycle, counters[i].CycleT, counters[i].sCycleT);
}
__Log("VIF0_STAT = %x, VIF1_STAT = %x\n", psHu32(0x3800), psHu32(0x3C00));
__Log("ipu %x %x %x %x; bp: %x %x %x %x\n", psHu32(0x2000), psHu32(0x2010), psHu32(0x2020), psHu32(0x2030), g_BP.BP, g_BP.bufferhasnew, g_BP.FP, g_BP.IFC);
__Log("gif: %x %x %x\n", psHu32(0x3000), psHu32(0x3010), psHu32(0x3020));
__Log("VIF0_STAT = %x, VIF1_STAT = %x", psHu32(0x3800), psHu32(0x3C00));
__Log("ipu %x %x %x %x; bp: %x %x %x %x", psHu32(0x2000), psHu32(0x2010), psHu32(0x2020), psHu32(0x2030), g_BP.BP, g_BP.bufferhasnew, g_BP.FP, g_BP.IFC);
__Log("gif: %x %x %x", psHu32(0x3000), psHu32(0x3010), psHu32(0x3020));
for(i = 0; i < ARRAYSIZE(dmacs); ++i) {
DMACh* p = (DMACh*)(PS2MEM_HW+dmacs[i]);
__Log("dma%d c%x m%x q%x t%x s%x\n", i, p->chcr, p->madr, p->qwc, p->tadr, p->sadr);
__Log("dma%d c%x m%x q%x t%x s%x", i, p->chcr, p->madr, p->qwc, p->tadr, p->sadr);
}
__Log("dmac %x %x %x %x\n", psHu32(DMAC_CTRL), psHu32(DMAC_STAT), psHu32(DMAC_RBSR), psHu32(DMAC_RBOR));
__Log("intc %x %x\n", psHu32(INTC_STAT), psHu32(INTC_MASK));
__Log("sif: %x %x %x %x %x\n", psHu32(0xf200), psHu32(0xf220), psHu32(0xf230), psHu32(0xf240), psHu32(0xf260));
__Log("dmac %x %x %x %x", psHu32(DMAC_CTRL), psHu32(DMAC_STAT), psHu32(DMAC_RBSR), psHu32(DMAC_RBOR));
__Log("intc %x %x", psHu32(INTC_STAT), psHu32(INTC_MASK));
__Log("sif: %x %x %x %x %x", psHu32(0xf200), psHu32(0xf220), psHu32(0xf230), psHu32(0xf240), psHu32(0xf260));
#endif
}

28
pcsx2/x86/iR3000A.cpp
View File

@ -940,23 +940,23 @@ void iDumpPsxRegisters(u32 startpc, u32 temp)
int i;
const char* pstr = temp ? "t" : "";
__Log("%spsxreg: %x %x ra:%x k0: %x %x\n", pstr, startpc, psxRegs.cycle, psxRegs.GPR.n.ra, psxRegs.GPR.n.k0, *(int*)PSXM(0x13c128));
for(i = 0; i < 34; i+=2) __Log("%spsx%s: %x %x\n", pstr, disRNameGPR[i], psxRegs.GPR.r[i], psxRegs.GPR.r[i+1]);
__Log("%scycle: %x %x %x; counters %x %x\n", pstr, psxRegs.cycle, g_psxNextBranchCycle, EEsCycle,
__Log("%spsxreg: %x %x ra:%x k0: %x %x", pstr, startpc, psxRegs.cycle, psxRegs.GPR.n.ra, psxRegs.GPR.n.k0, *(int*)PSXM(0x13c128));
for(i = 0; i < 34; i+=2) __Log("%spsx%s: %x %x", pstr, disRNameGPR[i], psxRegs.GPR.r[i], psxRegs.GPR.r[i+1]);
__Log("%scycle: %x %x %x; counters %x %x", pstr, psxRegs.cycle, g_psxNextBranchCycle, EEsCycle,
psxNextsCounter, psxNextCounter);
__Log("psxdma%d c%x b%x m%x t%x\n", 2, HW_DMA2_CHCR, HW_DMA2_BCR, HW_DMA2_MADR, HW_DMA2_TADR);
__Log("psxdma%d c%x b%x m%x\n", 3, HW_DMA3_CHCR, HW_DMA3_BCR, HW_DMA3_MADR);
__Log("psxdma%d c%x b%x m%x t%x\n", 4, HW_DMA4_CHCR, HW_DMA4_BCR, HW_DMA4_MADR, HW_DMA4_TADR);
__Log("psxdma%d c%x b%x m%x\n", 6, HW_DMA6_CHCR, HW_DMA6_BCR, HW_DMA6_MADR);
__Log("psxdma%d c%x b%x m%x\n", 7, HW_DMA7_CHCR, HW_DMA7_BCR, HW_DMA7_MADR);
__Log("psxdma%d c%x b%x m%x\n", 8, HW_DMA8_CHCR, HW_DMA8_BCR, HW_DMA8_MADR);
__Log("psxdma%d c%x b%x m%x t%x\n", 9, HW_DMA9_CHCR, HW_DMA9_BCR, HW_DMA9_MADR, HW_DMA9_TADR);
__Log("psxdma%d c%x b%x m%x\n", 10, HW_DMA10_CHCR, HW_DMA10_BCR, HW_DMA10_MADR);
__Log("psxdma%d c%x b%x m%x\n", 11, HW_DMA11_CHCR, HW_DMA11_BCR, HW_DMA11_MADR);
__Log("psxdma%d c%x b%x m%x\n", 12, HW_DMA12_CHCR, HW_DMA12_BCR, HW_DMA12_MADR);
__Log("psxdma%d c%x b%x m%x t%x", 2, HW_DMA2_CHCR, HW_DMA2_BCR, HW_DMA2_MADR, HW_DMA2_TADR);
__Log("psxdma%d c%x b%x m%x", 3, HW_DMA3_CHCR, HW_DMA3_BCR, HW_DMA3_MADR);
__Log("psxdma%d c%x b%x m%x t%x", 4, HW_DMA4_CHCR, HW_DMA4_BCR, HW_DMA4_MADR, HW_DMA4_TADR);
__Log("psxdma%d c%x b%x m%x", 6, HW_DMA6_CHCR, HW_DMA6_BCR, HW_DMA6_MADR);
__Log("psxdma%d c%x b%x m%x", 7, HW_DMA7_CHCR, HW_DMA7_BCR, HW_DMA7_MADR);
__Log("psxdma%d c%x b%x m%x", 8, HW_DMA8_CHCR, HW_DMA8_BCR, HW_DMA8_MADR);
__Log("psxdma%d c%x b%x m%x t%x", 9, HW_DMA9_CHCR, HW_DMA9_BCR, HW_DMA9_MADR, HW_DMA9_TADR);
__Log("psxdma%d c%x b%x m%x", 10, HW_DMA10_CHCR, HW_DMA10_BCR, HW_DMA10_MADR);
__Log("psxdma%d c%x b%x m%x", 11, HW_DMA11_CHCR, HW_DMA11_BCR, HW_DMA11_MADR);
__Log("psxdma%d c%x b%x m%x", 12, HW_DMA12_CHCR, HW_DMA12_BCR, HW_DMA12_MADR);
for(i = 0; i < 7; ++i)
__Log("%scounter%d: mode %x count %I64x rate %x scycle %x target %I64x\n", pstr, i, psxCounters[i].mode, psxCounters[i].count, psxCounters[i].rate, psxCounters[i].sCycleT, psxCounters[i].target);
__Log("%scounter%d: mode %x count %I64x rate %x scycle %x target %I64x", pstr, i, psxCounters[i].mode, psxCounters[i].count, psxCounters[i].rate, psxCounters[i].sCycleT, psxCounters[i].target);
#endif
}

2
pcsx2/x86/iVU1micro.cpp
View File

@ -97,7 +97,7 @@ namespace VU1micro
#ifdef _DEBUG
static u32 vuprogcount = 0;
vuprogcount++;
if( vudump & 8 ) __Log("start vu1: %x %x\n", VU1.VI[ REG_TPC ].UL, vuprogcount);
if( vudump & 8 ) __Log("start vu1: %x %x", VU1.VI[ REG_TPC ].UL, vuprogcount);
#endif
if((VU0.VI[REG_VPU_STAT].UL & 0x100) == 0){

10
pcsx2/x86/iVUmicro.cpp
View File

@ -144,13 +144,13 @@ void _recvuFMACflush(VURegs * VU, bool intermediate) {
if( intermediate ) {
if ((vucycle - VU->fmac[i].sCycle) > VU->fmac[i].Cycle) {
// VUM_LOG("flushing FMAC pipe[%d]\n", i);
// VUM_LOG("flushing FMAC pipe[%d]", i);
VU->fmac[i].enable = 0;
}
}
else {
if ((vucycle - VU->fmac[i].sCycle) >= VU->fmac[i].Cycle) {
// VUM_LOG("flushing FMAC pipe[%d]\n", i);
// VUM_LOG("flushing FMAC pipe[%d]", i);
VU->fmac[i].enable = 0;
}
}
@ -199,13 +199,13 @@ void _recvuIALUflush(VURegs * VU, bool intermediate) {
if( intermediate ) {
if ((vucycle - VU->ialu[i].sCycle) > VU->ialu[i].Cycle) {
// VUM_LOG("flushing IALU pipe[%d]\n", i);
// VUM_LOG("flushing IALU pipe[%d]", i);
VU->ialu[i].enable = 0;
}
}
else {
if ((vucycle - VU->ialu[i].sCycle) >= VU->ialu[i].Cycle) {
// VUM_LOG("flushing IALU pipe[%d]\n", i);
// VUM_LOG("flushing IALU pipe[%d]", i);
VU->ialu[i].enable = 0;
}
}
@ -292,7 +292,7 @@ void _recvuFMACAdd(VURegs * VU, int reg, int xyzw) {
}
if (i==8) Console::Error("*PCSX2*: error , out of fmacs");
// VUM_LOG("adding FMAC pipe[%d]; reg %d\n", i, reg);
// VUM_LOG("adding FMAC pipe[%d]; reg %d", i, reg);
VU->fmac[i].enable = 1;
VU->fmac[i].sCycle = vucycle;

10
plugins/zerogs/opengl/zerogs.h
View File

@ -111,6 +111,16 @@ static __forceinline const char *error_name(int err)
}
}
#define GL_ERROR_LOG() \
{ \
GLenum myGLerror = glGetError(); \
\
if( myGLerror != GL_NO_ERROR ) \
{ \
ERROR_LOG("%s:%d: gl error %s\n", __FILE__, (int)__LINE__, error_name(myGLerror)); \
} \
}\
#define GL_REPORT_ERROR() \
{ \
err = glGetError(); \