mirror of https://github.com/PCSX2/pcsx2.git
Various VifDma cleanups.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1296 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42
parent
4fc4a634b3
commit
0028fefcbc
146
pcsx2/VifDma.cpp
146
pcsx2/VifDma.cpp
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@ -339,8 +339,7 @@ static int VIFalign(u32 *data, vifCode *v, unsigned int size, const unsigned int
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const VIFUnpackFuncTable *ft;
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VURegs * VU;
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u8 *cdata = (u8*)data;
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#ifdef _DEBUG
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u32 memsize = VIFdmanum ? 0x4000 : 0x1000;
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#endif
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@ -453,7 +452,6 @@ static int VIFalign(u32 *data, vifCode *v, unsigned int size, const unsigned int
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VIFUNPACK_LOG("Aligning packet done size = %d offset %d addr %x", size, vifRegs->offset, vif->tag.addr);
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}
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}
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if (vif->cl != 0 || (size & 0xf)) //Check alignment for SSE unpacks
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{
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@ -544,7 +542,6 @@ static int VIFalign(u32 *data, vifCode *v, unsigned int size, const unsigned int
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return size>>2;
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}
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static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned int VIFdmanum)
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{
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u32 *dest;
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@ -554,9 +551,10 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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VURegs * VU;
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u8 *cdata = (u8*)data;
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u32 tempsize = 0;
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const u32 memlimit = (VIFdmanum ? 0x4000 : 0x1000);
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#ifdef _DEBUG
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u32 memsize = VIFdmanum ? 0x4000 : 0x1000;
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u32 memsize = memlimit;
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#endif
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_mm_prefetch((char*)data, _MM_HINT_NTA);
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@ -608,10 +606,10 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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#ifdef _DEBUG
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static int s_count = 0;
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#endif
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if(v->addr >= (u32)(VIFdmanum ? 0x4000 : 0x1000))
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if (v->addr >= memlimit)
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{
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//DevCon::Notice("Overflown at the start");
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v->addr &= (u32)(VIFdmanum ? 0x3fff : 0xfff);
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v->addr &= (memlimit - 1);
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dest = (u32*)(VU->Mem + v->addr);
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}
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@ -620,12 +618,11 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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((vifRegs->cycle.cl - vifRegs->cycle.wl) * 16)) + (tempsize * 16);
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//Sanity Check (memory overflow)
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if(tempsize > (u32)(VIFdmanum ? 0x4000 : 0x1000))
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if (tempsize > memlimit)
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{
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if(((vifRegs->cycle.cl != vifRegs->cycle.wl) && ((u32)(VIFdmanum ? 0x4000 : 0x1000) + ((vifRegs->cycle.cl - vifRegs->cycle.wl) * 16)) == tempsize)
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|| tempsize == (u32)(VIFdmanum ? 0x4000 : 0x1000))
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if (((vifRegs->cycle.cl != vifRegs->cycle.wl) &&
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(memlimit + ((vifRegs->cycle.cl - vifRegs->cycle.wl) * 16)) == tempsize) ||
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(tempsize == memlimit))
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{
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//Its a red herring! so ignore it! SSE unpacks will be much quicker
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tempsize = 0;
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@ -636,8 +633,11 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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tempsize = size;
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size = 0;
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}
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} else tempsize = 0;
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}
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else
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{
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tempsize = 0;
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}
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if (size >= ft->gsize)
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{
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@ -673,7 +673,8 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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}
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#endif
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if ((vifRegs->cycle.cl == 0) || (vifRegs->cycle.wl == 0) || ((vifRegs->cycle.cl == vifRegs->cycle.wl) && !(vifRegs->code & 0x10000000)))
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if ((vifRegs->cycle.cl == 0) || (vifRegs->cycle.wl == 0) ||
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((vifRegs->cycle.cl == vifRegs->cycle.wl) && !(vifRegs->code & 0x10000000)))
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{
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oldcycle = *(u32*) & vifRegs->cycle;
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vifRegs->cycle.cl = vifRegs->cycle.wl = 1;
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@ -745,9 +746,9 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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while ((tempsize >= ft->gsize) && (vifRegs->num > 0))
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{
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if(v->addr >= (u32)(VIFdmanum ? 0x4000 : 0x1000))
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if(v->addr >= memlimit)
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{
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v->addr &= (u32)(VIFdmanum ? 0x3fff : 0xfff);
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v->addr &= (memlimit - 1);
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dest = (u32*)(VU->Mem + v->addr);
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}
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@ -778,9 +779,9 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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vifRow[2] = vifRegs->r2;
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vifRow[3] = vifRegs->r3;
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}
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if(v->addr >= (u32)(VIFdmanum ? 0x4000 : 0x1000))
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if(v->addr >= memlimit)
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{
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v->addr &= (u32)(VIFdmanum ? 0x3fff : 0xfff);
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v->addr &= (memlimit - 1);
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dest = (u32*)(VU->Mem + v->addr);
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}
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if(tempsize > 0) size = tempsize;
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@ -828,11 +829,13 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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VIF_LOG("Out of Filling write data");
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break;
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}
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func(dest, (u32*)cdata, ft->qsize);
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cdata += ft->gsize;
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size -= ft->gsize;
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vif->cl++;
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vifRegs->num--;
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if (vif->cl == vifRegs->cycle.wl)
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{
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vif->cl = 0;
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@ -866,6 +869,7 @@ static void vuExecMicro(u32 addr, const u32 VIFdmanum)
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VU = &VU1;
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vif1FLUSH();
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}
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if (VU->vifRegs->itops > (VIFdmanum ? 0x3ffu : 0xffu))
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Console::WriteLn("VIF%d ITOP overrun! %x", params VIFdmanum, VU->vifRegs->itops);
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@ -1060,19 +1064,24 @@ static int __fastcall Vif0TransMPG(u32 *data) // MPG
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if (vif0.vifpacketsize < vif0.tag.size)
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{
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if((vif0.tag.addr + vif0.vifpacketsize) > 0x1000) DevCon::Notice("Vif0 MPG Split Overflow");
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vif0mpgTransfer(vif0.tag.addr, data, vif0.vifpacketsize);
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vif0.tag.addr += vif0.vifpacketsize << 2;
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vif0.tag.size -= vif0.vifpacketsize;
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return vif0.vifpacketsize;
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}
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else
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{
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int ret;
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if((vif0.tag.addr + vif0.tag.size) > 0x1000) DevCon::Notice("Vif0 MPG Overflow");
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vif0mpgTransfer(vif0.tag.addr, data, vif0.tag.size);
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ret = vif0.tag.size;
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vif0.tag.size = 0;
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vif0.cmd = 0;
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return ret;
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}
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}
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@ -1090,10 +1099,13 @@ static int __fastcall Vif0TransUnpack(u32 *data) // UNPACK
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vif0.tag.size -= vif0.vifpacketsize - VIFalign(data, &vif0.tag, vif0.vifpacketsize, VIF0dmanum);
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ret = ret - vif0.tag.size;
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data += ret;
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if(vif0.vifpacketsize > 0) VIFunpack(data, &vif0.tag, vif0.vifpacketsize - ret, VIF0dmanum);
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ProcessMemSkip((vif0.vifpacketsize - ret) << 2, (vif0.cmd & 0xf), VIF0dmanum);
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vif0.tag.size -= (vif0.vifpacketsize - ret);
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FreezeXMMRegs(0);
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return vif0.vifpacketsize;
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}
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/* size is less that the total size, transfer is 'in pieces' */
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@ -1391,10 +1403,9 @@ int _chainVIF0()
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{
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VIF_LOG("dmaIrq Set\n");
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vif0.done = true;
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return (vif0.done)?1:0; //End Transfer
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vif0.done = true; //End Transfer
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}
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return (vif0.done)?1:0; //Return Done
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return (vif0.done) ? 1: 0; //Return Done
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}
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void vif0Interrupt()
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@ -1414,6 +1425,7 @@ void vif0Interrupt()
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vif0ch->chcr &= ~0x100;
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return;
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}
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if (vif0ch->qwc > 0 || vif0.irqoffset > 0)
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{
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if (vif0.stallontag)
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@ -1448,6 +1460,7 @@ void vif0Interrupt()
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if (vif0ch->qwc > 0) Console::WriteLn("VIF0 Ending with QWC left");
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if (vif0.cmd != 0) Console::WriteLn("vif0.cmd still set %x", params vif0.cmd);
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vif0ch->chcr &= ~0x100;
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hwDmacIrq(DMAC_VIF0);
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vif0Regs->stat &= ~0xF000000; // FQC=0
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@ -1508,6 +1521,7 @@ void dmaVIF0()
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vif0.vifstalled = true;
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return;
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}
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vif0.done = true;
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CPU_INT(0, g_vifCycles);
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return;
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@ -1522,7 +1536,7 @@ void vif0Write32(u32 mem, u32 value)
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{
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switch (mem)
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{
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case 0x10003830: // MARK
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case VIF0_MARK:
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VIF_LOG("VIF0_MARK write32 0x%8.8x", value);
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/* Clear mark flag in VIF0_STAT and set mark with 'value' */
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@ -1530,7 +1544,7 @@ void vif0Write32(u32 mem, u32 value)
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vif0Regs->mark = value;
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break;
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case 0x10003810: // FBRST
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case VIF0_FBRST:
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VIF_LOG("VIF0_FBRST write32 0x%8.8x", value);
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if (value & 0x1)
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@ -1546,6 +1560,7 @@ void vif0Write32(u32 mem, u32 value)
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vif0Regs->err = 0;
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vif0Regs->stat &= ~(0xF000000 | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
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}
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if (value & 0x2)
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{
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/* Force Break the VIF */
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@ -1555,7 +1570,8 @@ void vif0Write32(u32 mem, u32 value)
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vif0Regs->stat &= ~VIF0_STAT_VPS;
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vif0.vifstalled = true;
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Console::WriteLn("vif0 force break");
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}
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}
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if (value & 0x4)
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{
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/* Stop VIF */
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@ -1565,6 +1581,7 @@ void vif0Write32(u32 mem, u32 value)
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vif0Regs->stat &= ~VIF0_STAT_VPS;
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vif0.vifstalled = true;
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}
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if (value & 0x8)
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{
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bool cancel = false;
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@ -1594,7 +1611,7 @@ void vif0Write32(u32 mem, u32 value)
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}
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break;
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case 0x10003820:
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case VIF0_ERR:
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// ERR
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VIF_LOG("VIF0_ERR write32 0x%8.8x", value);
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@ -1604,11 +1621,11 @@ void vif0Write32(u32 mem, u32 value)
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default:
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Console::WriteLn("Unknown Vif0 write to %x", params mem);
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if (mem >= 0x10003900 && mem < 0x10003980)
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if (mem >= VIF0_R0 && mem < 0x10003980) // mem <= VIF0_C3?
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{
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assert((mem&0xf) == 0);
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if (mem < 0x10003940)
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if (mem < VIF0_C0)
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g_vifRow0[(mem>>4)&3] = value;
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else
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g_vifCol0[(mem>>4)&3] = value;
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@ -1974,18 +1991,19 @@ static int __fastcall Vif1TransUnpack(u32 *data)
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Vif1 CMD Base Commands
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// fixme: Global variables should not have the same name as local variables, and this probably shouldn't be local anyways.
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int transferred = 0;
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static void Vif1CMDNop() // NOP
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{
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDSTCycl() // STCYCL
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{
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vif1Regs->cycle.cl = (u8)vif1Regs->code;
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vif1Regs->cycle.wl = (u8)(vif1Regs->code >> 8);
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDOffset() // OFFSET
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{
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vif1Regs->ofst = vif1Regs->code & 0x3ff;
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@ -1993,11 +2011,13 @@ static void Vif1CMDOffset() // OFFSET
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vif1Regs->tops = vif1Regs->base;
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDBase() // BASE
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{
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vif1Regs->base = vif1Regs->code & 0x3ff;
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDITop() // ITOP
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{
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vif1Regs->itops = vif1Regs->code & 0x3ff;
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@ -2010,10 +2030,8 @@ static void Vif1CMDSTMod() // STMOD
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDMskPath3() // MSKPATH3
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{
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vif1Regs->mskpath3 = (vif1Regs->code >> 15) & 0x1;
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//Console::WriteLn("VIF MSKPATH3 %x", params vif1Regs->mskpath3);
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@ -2036,11 +2054,8 @@ static void Vif1CMDMark() // MARK
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDFlush() // FLUSH/E/A
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{
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vif1FLUSH();
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if((vif1.cmd & 0x7f) == 0x13)
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@ -2053,21 +2068,25 @@ static void Vif1CMDFlush() // FLUSH/E/A
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDMSCALF() //MSCAL/F
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{
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vif1FLUSH();
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vuExecMicro((u16)(vif1Regs->code) << 3, VIF1dmanum);
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDMSCNT() // MSCNT
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{
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vuExecMicro(-1, VIF1dmanum);
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vif1.cmd &= ~0x7f;
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}
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static void Vif1CMDSTMask() // STMASK
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{
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vif1.tag.size = 1;
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}
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static void Vif1CMDSTRowCol() // STROW / STCOL
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{
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vif1.tag.addr = 0;
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@ -2086,8 +2105,6 @@ static void Vif1CMDMPGTransfer() // MPG
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vif1.tag.size = vifNum * 2;
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}
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static void Vif1CMDDirectHL() // DIRECT/HL
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{
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int vifImm;
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@ -2110,8 +2127,8 @@ static void Vif1CMDDirectHL() // DIRECT/HL
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}
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psHu32(GIF_STAT) |= (GIF_STAT_APATH2 | GIF_STAT_OPH);
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}
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static void Vif1CMDNull() // invalid opcode
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{
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// if ME1, then force the vif to interrupt
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@ -2170,7 +2187,7 @@ void (*Vif1CMDTLB[82])() =
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int VIF1transfer(u32 *data, int size, int istag)
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{
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int ret;
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transferred = vif1.vifstalled ? vif1.irqoffset : 0; // irqoffset necessary to add up the right qws, or else will spin (spiderman)
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int transferred = vif1.vifstalled ? vif1.irqoffset : 0; // irqoffset necessary to add up the right qws, or else will spin (spiderman)
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VIF_LOG("VIF1transfer: size %x (vif1.cmd %x)", size, vif1.cmd);
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@ -2191,7 +2208,9 @@ int VIF1transfer(u32 *data, int size, int istag)
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}
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}
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if(vif1Regs->stat & VIF1_STAT_VGW) break;
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if (vif1.cmd)
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{
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vif1Regs->stat |= VIF1_STAT_VPS_T; //Decompression has started
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@ -2263,7 +2282,7 @@ int VIF1transfer(u32 *data, int size, int istag)
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{
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vif1.vifstalled = true;
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||||
|
||||
if (((vif1Regs->code >> 24) & 0x7f) != 0x7)vif1Regs->stat |= VIF1_STAT_VIS; // Note: commenting this out fixes WALL-E
|
||||
if (((vif1Regs->code >> 24) & 0x7f) != 0x7) vif1Regs->stat |= VIF1_STAT_VIS; // Note: commenting this out fixes WALL-E
|
||||
|
||||
if (vif1ch->qwc == 0 && (vif1.irqoffset == 0 || istag == 1))
|
||||
vif1.inprogress = 0;
|
||||
|
|
@ -2326,6 +2345,7 @@ void vif1TransferFromMemory()
|
|||
// completely and execute the transfer there-after.
|
||||
|
||||
FreezeXMMRegs(1);
|
||||
|
||||
if (GSreadFIFO2 == NULL)
|
||||
{
|
||||
for (size = vif1ch->qwc; size > 0; --size)
|
||||
|
|
@ -2349,8 +2369,8 @@ void vif1TransferFromMemory()
|
|||
psHu64(0x5000) = pMem[2*vif1ch->qwc-2];
|
||||
psHu64(0x5008) = pMem[2*vif1ch->qwc-1];
|
||||
}
|
||||
|
||||
FreezeXMMRegs(0);
|
||||
|
||||
|
||||
g_vifCycles += vif1ch->qwc * 2;
|
||||
vif1ch->madr += vif1ch->qwc * 16; // mgs3 scene changes
|
||||
|
|
@ -2368,7 +2388,7 @@ int _VIF1chain()
|
|||
return 0;
|
||||
}
|
||||
|
||||
if (vif1.dmamode == 1)
|
||||
if (vif1.dmamode == VIF_NORMAL_MEM_MODE)
|
||||
{
|
||||
vif1TransferFromMemory();
|
||||
vif1.inprogress = 0;
|
||||
|
|
@ -2398,14 +2418,14 @@ __forceinline void vif1SetupTransfer()
|
|||
{
|
||||
switch (vif1.dmamode)
|
||||
{
|
||||
case 0: //Normal
|
||||
case 1: //Normal (From memory)
|
||||
case VIF_NORMAL_MODE: //Normal
|
||||
case VIF_NORMAL_MEM_MODE: //Normal (From memory)
|
||||
vif1.inprogress = 1;
|
||||
vif1.done = true;
|
||||
g_vifCycles = 2;
|
||||
break;
|
||||
|
||||
case 2: //Chain
|
||||
case VIF_CHAIN_MODE: //Chain
|
||||
int id;
|
||||
int ret;
|
||||
|
||||
|
|
@ -2490,7 +2510,6 @@ __forceinline void vif1Interrupt()
|
|||
|
||||
}
|
||||
|
||||
|
||||
if ((vif1ch->chcr & 0x100) == 0) Console::WriteLn("Vif1 running when CHCR == %x", params vif1ch->chcr);
|
||||
|
||||
if (vif1.irq && vif1.tag.size == 0)
|
||||
|
|
@ -2556,7 +2575,6 @@ __forceinline void vif1Interrupt()
|
|||
|
||||
void dmaVIF1()
|
||||
{
|
||||
|
||||
VIF_LOG("dmaVIF1 chcr = %lx, madr = %lx, qwc = %lx\n"
|
||||
" tadr = %lx, asr0 = %lx, asr1 = %lx",
|
||||
vif1ch->chcr, vif1ch->madr, vif1ch->qwc,
|
||||
|
|
@ -2564,7 +2582,6 @@ void dmaVIF1()
|
|||
|
||||
g_vifCycles = 0;
|
||||
vif1.inprogress = 0;
|
||||
|
||||
|
||||
if (((psHu32(DMAC_CTRL) & 0xC) == 0x8)) // VIF MFIFO
|
||||
{
|
||||
|
|
@ -2581,7 +2598,6 @@ void dmaVIF1()
|
|||
}
|
||||
#endif
|
||||
|
||||
|
||||
if (!(vif1ch->chcr & 0x4) || vif1ch->qwc > 0) // Normal Mode
|
||||
{
|
||||
|
||||
|
|
@ -2589,29 +2605,30 @@ void dmaVIF1()
|
|||
Console::WriteLn("DMA Stall Control on VIF1 normal");
|
||||
|
||||
if ((vif1ch->chcr & 0x1)) // to Memory
|
||||
vif1.dmamode = 0;
|
||||
vif1.dmamode = VIF_NORMAL_MODE;
|
||||
else
|
||||
vif1.dmamode = 1;
|
||||
vif1.dmamode = VIF_NORMAL_MEM_MODE;
|
||||
}
|
||||
else
|
||||
{
|
||||
vif1.dmamode = 2;
|
||||
vif1.dmamode = VIF_CHAIN_MODE;
|
||||
}
|
||||
|
||||
if(vif1.dmamode != 1)vif1Regs->stat |= 0x10000000; // FQC=16
|
||||
else vif1Regs->stat |= min((u16)16, vif1ch->qwc) << 24; // FQC=16
|
||||
if(vif1.dmamode != VIF_NORMAL_MEM_MODE)
|
||||
vif1Regs->stat |= 0x10000000; // FQC=16
|
||||
else
|
||||
vif1Regs->stat |= min((u16)16, vif1ch->qwc) << 24; // FQC=16
|
||||
|
||||
// Chain Mode
|
||||
vif1.done = false;
|
||||
vif1Interrupt();
|
||||
}
|
||||
|
||||
|
||||
void vif1Write32(u32 mem, u32 value)
|
||||
{
|
||||
switch (mem)
|
||||
{
|
||||
case 0x10003c30: // MARK
|
||||
case VIF1_MARK:
|
||||
VIF_LOG("VIF1_MARK write32 0x%8.8x", value);
|
||||
|
||||
/* Clear mark flag in VIF1_STAT and set mark with 'value' */
|
||||
|
|
@ -2619,7 +2636,7 @@ void vif1Write32(u32 mem, u32 value)
|
|||
vif1Regs->mark = value;
|
||||
break;
|
||||
|
||||
case 0x10003c10: // FBRST
|
||||
case VIF1_FBRST: // FBRST
|
||||
VIF_LOG("VIF1_FBRST write32 0x%8.8x", value);
|
||||
|
||||
if (value & 0x1)
|
||||
|
|
@ -2635,6 +2652,7 @@ void vif1Write32(u32 mem, u32 value)
|
|||
vif1.inprogress = 0;
|
||||
vif1Regs->stat &= ~(0x1F800000 | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
|
||||
}
|
||||
|
||||
if (value & 0x2)
|
||||
{
|
||||
/* Force Break the VIF */
|
||||
|
|
@ -2645,6 +2663,7 @@ void vif1Write32(u32 mem, u32 value)
|
|||
vif1.vifstalled = true;
|
||||
Console::WriteLn("vif1 force break");
|
||||
}
|
||||
|
||||
if (value & 0x4)
|
||||
{
|
||||
/* Stop VIF */
|
||||
|
|
@ -2655,6 +2674,7 @@ void vif1Write32(u32 mem, u32 value)
|
|||
cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
|
||||
vif1.vifstalled = true;
|
||||
}
|
||||
|
||||
if (value & 0x8)
|
||||
{
|
||||
bool cancel = false;
|
||||
|
|
@ -2690,15 +2710,15 @@ void vif1Write32(u32 mem, u32 value)
|
|||
}
|
||||
break;
|
||||
|
||||
case 0x10003c20: // ERR
|
||||
case VIF1_ERR: // ERR
|
||||
VIF_LOG("VIF1_ERR write32 0x%8.8x", value);
|
||||
|
||||
/* Set VIF1_ERR with 'value' */
|
||||
vif1Regs->err = value;
|
||||
break;
|
||||
|
||||
case 0x10003c00: // STAT
|
||||
VIF_LOG("VIF1_STAT write32 0x%8.8x", value);
|
||||
case VIF1_STAT: // STAT
|
||||
VIF_LOG("VIF1_STAT write32 0x%8.8x", value);
|
||||
|
||||
#ifdef PCSX2_DEVBUILD
|
||||
/* Only FDR bit is writable, so mask the rest */
|
||||
|
|
@ -2726,16 +2746,16 @@ void vif1Write32(u32 mem, u32 value)
|
|||
}
|
||||
break;
|
||||
|
||||
case 0x10003c50: // MODE
|
||||
case VIF1_MODE: // MODE
|
||||
vif1Regs->mode = value;
|
||||
break;
|
||||
|
||||
default:
|
||||
Console::WriteLn("Unknown Vif1 write to %x", params mem);
|
||||
if ((mem >= 0x10003d00) && (mem < 0x10003d80))
|
||||
if ((mem >= VIF1_R0) && (mem < 0x10003d80)) // mem <= VIF1_C3?
|
||||
{
|
||||
assert((mem&0xf) == 0);
|
||||
if (mem < 0x10003d40)
|
||||
if (mem < VIF1_C0)
|
||||
g_vifRow1[(mem>>4)&3] = value;
|
||||
else
|
||||
g_vifCol1[(mem>>4)&3] = value;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,61 @@
|
|||
#ifndef __VIFDMA_H__
|
||||
#define __VIFDMA_H__
|
||||
|
||||
enum VifModes
|
||||
{
|
||||
VIF_NORMAL_MODE = 0,
|
||||
VIF_NORMAL_MEM_MODE = 1,
|
||||
VIF_CHAIN_MODE = 2
|
||||
};
|
||||
|
||||
enum VifMemoryLocations
|
||||
{
|
||||
VIF0_STAT = 0x10003800,
|
||||
VIF0_FBRST = 0x10003810,
|
||||
VIF0_ERR = 0x10003820,
|
||||
VIF0_MARK = 0x10003830,
|
||||
VIF0_CYCLE = 0x10003840,
|
||||
VIF0_MODE = 0x10003850,
|
||||
VIF0_NUM = 0x10003860,
|
||||
VIF0_MASK = 0x10003870,
|
||||
VIF0_CODE = 0x10003880,
|
||||
VIF0_ITOPS = 0x10003890,
|
||||
VIF0_ITOP = 0x100038d0,
|
||||
VIF0_TOP = 0x100038e0,
|
||||
VIF0_R0 = 0x10003900,
|
||||
VIF0_R1 = 0x10003910,
|
||||
VIF0_R2 = 0x10003920,
|
||||
VIF0_R3 = 0x10003930,
|
||||
VIF0_C0 = 0x10003940,
|
||||
VIF0_C1 = 0x10003950,
|
||||
VIF0_C2 = 0x10003960,
|
||||
VIF0_C3 = 0x10003970,
|
||||
|
||||
VIF1_STAT = 0x10003c00,
|
||||
VIF1_FBRST = 0x10003c10,
|
||||
VIF1_ERR = 0x10003c20,
|
||||
VIF1_MARK = 0x10003c30,
|
||||
VIF1_CYCLE = 0x10003c40,
|
||||
VIF1_MODE = 0x10003c50,
|
||||
VIF1_NUM = 0x10003c60,
|
||||
VIF1_MASK = 0x10003c70,
|
||||
VIF1_CODE = 0x10003c80,
|
||||
VIF1_ITOPS = 0x10003c90,
|
||||
VIF1_BASE = 0x10003ca0,
|
||||
VIF1_OFST = 0x10003cb0,
|
||||
VIF1_TOPS = 0x10003cc0,
|
||||
VIF1_ITOP = 0x10003cd0,
|
||||
VIF1_TOP = 0x10003ce0,
|
||||
VIF1_R0 = 0x10003d00,
|
||||
VIF1_R1 = 0x10003d10,
|
||||
VIF1_R2 = 0x10003d20,
|
||||
VIF1_R3 = 0x10003d30,
|
||||
VIF1_C0 = 0x10003d40,
|
||||
VIF1_C1 = 0x10003d50,
|
||||
VIF1_C2 = 0x10003d60,
|
||||
VIF1_C3 = 0x10003d70
|
||||
};
|
||||
|
||||
struct vifCode {
|
||||
u32 addr;
|
||||
u32 size;
|
||||
|
|
|
|||
Loading…
Reference in New Issue