2023-12-22 11:57:49 +00:00
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// SPDX-FileCopyrightText: 2002-2023 PCSX2 Dev Team
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// SPDX-License-Identifier: LGPL-3.0+
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2009-04-16 01:39:38 +00:00
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#pragma once
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2016-11-12 15:28:37 +00:00
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namespace x86Emitter
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{
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2009-11-06 21:45:30 +00:00
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2021-09-06 18:28:26 +00:00
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// Implementations here cover SHLD and SHRD.
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// --------------------------------------------------------------------------------------
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// xImpl_DowrdShift
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// --------------------------------------------------------------------------------------
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// I use explicit method declarations here instead of templates, in order to provide
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// *only* 32 and 16 bit register operand forms (8 bit registers are not valid in SHLD/SHRD).
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//
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// Optimization Note: Imm shifts by 0 are ignore (no code generated). This is a safe optimization
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// because shifts by 0 do *not* affect flags status (intel docs cited).
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//
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struct xImpl_DwordShift
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{
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u16 OpcodeBase;
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void operator()(const xRegister16or32or64& to, const xRegister16or32or64& from, const xRegisterCL& clreg) const;
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void operator()(const xRegister16or32or64& to, const xRegister16or32or64& from, u8 shiftcnt) const;
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void operator()(const xIndirectVoid& dest, const xRegister16or32or64& from, const xRegisterCL& clreg) const;
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void operator()(const xIndirectVoid& dest, const xRegister16or32or64& from, u8 shiftcnt) const;
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};
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2009-04-16 01:39:38 +00:00
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2016-11-12 15:28:37 +00:00
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} // End namespace x86Emitter
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