mirror of https://github.com/PCSX2/pcsx2.git
74 lines
2.9 KiB
C
74 lines
2.9 KiB
C
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//------------------------------------------------------------------------
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// File: regs.h
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// Author: Tony Saveski, t_saveski@yahoo.com
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// Notes: Playstation 2 Register Definitions
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//------------------------------------------------------------------------
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#ifndef R5900_REGS_H
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#define R5900_REGS_H
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// MIPS CPU Registsers
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#define zero $0 // Always 0
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#define at $1 // Assembler temporary
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#define v0 $2 // Function return
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#define v1 $3 //
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#define a0 $4 // Function arguments
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#define a1 $5
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#define a2 $6
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#define a3 $7
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#define t0 $8 // Temporaries. No need
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#define t1 $9 // to preserve in your
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#define t2 $10 // functions.
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#define s0 $16 // Saved Temporaries.
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#define s1 $17 // Make sure to restore
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#define s2 $18 // to original value
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#define s3 $19 // if your function
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#define s4 $20 // changes their value.
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#define s5 $21
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#define s6 $22
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#define s7 $23
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#define t8 $24 // More Temporaries.
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#define t9 $25
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#define k0 $26 // Reserved for Kernel
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#define k1 $27
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#define gp $28 // Global Pointer
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#define sp $29 // Stack Pointer
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#define fp $30 // Frame Pointer
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#define ra $31 // Function Return Address
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// COP0
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#define Index $0 // Index into the TLB array
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#define Random $1 // Randomly generated index into the TLB array
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#define EntryLo0 $2 // Low-order portion of the TLB entry for..
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#define EntryLo1 $3 // Low-order portion of the TLB entry for
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#define Context $4 // Pointer to page table entry in memory
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#define PageMask $5 // Control for variable page size in TLB entries
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#define Wired $6 // Controls the number of fixed ("wired") TLB entries
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#define BadVAddr $8 // Address for the most recent address-related exception
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#define Count $9 // Processor cycle count
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#define EntryHi $10 // High-order portion of the TLB entry
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#define Compare $11 // Timer interrupt control
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#define Status $12 // Processor status and control
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#define Cause $13 // Cause of last general exception
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#define EPC $14 // Program counter at last exception
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#define PRId $15 // Processor identification and revision
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#define Config $16 // Configuration register
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#define LLAddr $17 // Load linked address
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#define WatchLo $18 // Watchpoint address Section 6.25 on
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#define WatchHi $19 // Watchpoint control
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#define Debug $23 // EJTAG Debug register
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#define DEPC $24 // Program counter at last EJTAG debug exception
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#define PerfCnt $25 // Performance counter interface
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#define ErrCtl $26 // Parity/ECC error control and status
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#define CacheErr $27 // Cache parity error control and status
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#define TagLo $28 // Low-order portion of cache tag interface
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#define TagHi $29 // High-order portion of cache tag interface
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#define ErrorPC $30 // Program counter at last error
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#define DEASVE $31 // EJTAG debug exception save register
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#endif // R5900_REGS_H
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