2015-08-04 21:52:48 +00:00
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#pragma once
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#include "../USB.h"
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#include "vl.h"
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#ifdef PCSX2_DEVBUILD
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# define DEBUG_OHCI
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#endif
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/* Dump packet contents. */
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//#define DEBUG_PACKET
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/* This causes frames to occur 1000x slower */
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//#define OHCI_TIME_WARP 1
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/* Number of Downstream Ports on the root hub. */
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#define OHCI_MAX_PORTS 2
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extern int64_t usb_frame_time;
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extern int64_t usb_bit_time;
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typedef struct OHCIPort {
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USBPort port;
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uint32_t ctrl;
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} OHCIPort;
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typedef uint32_t target_phys_addr_t;
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typedef struct {
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//USBBus bus;
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//qemu_irq irq;
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int mem;
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int num_ports;
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const char *name;
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//QEMUTimer *eof_timer;
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int64_t eof_timer;
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int64_t sof_time;
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/* OHCI state */
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/* Control partition */
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uint32_t ctl, status;
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uint32_t intr_status;
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uint32_t intr;
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/* memory pointer partition */
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uint32_t hcca;
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uint32_t ctrl_head, ctrl_cur;
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uint32_t bulk_head, bulk_cur;
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uint32_t per_cur;
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uint32_t done;
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int done_count;
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/* Frame counter partition */
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uint32_t fsmps:15;
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uint32_t fit:1;
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uint32_t fi:14;
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uint32_t frt:1;
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uint16_t frame_number;
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uint16_t padding;
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uint32_t pstart;
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uint32_t lst;
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/* Root Hub partition */
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uint32_t rhdesc_a, rhdesc_b;
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uint32_t rhstatus;
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OHCIPort rhport[OHCI_MAX_PORTS];
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/* PXA27x Non-OHCI events */
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uint32_t hstatus;
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uint32_t hmask;
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uint32_t hreset;
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uint32_t htest;
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/* SM501 local memory offset */
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target_phys_addr_t localmem_base;
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/* Active packets. */
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uint32_t old_ctl;
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USBPacket usb_packet;
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uint8_t usb_buf[8192];
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uint32_t async_td;
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int async_complete;
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} OHCIState;
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/* Host Controller Communications Area */
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struct ohci_hcca {
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uint32_t intr[32];
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uint16_t frame, pad;
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uint32_t done;
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};
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static void ohci_bus_stop(OHCIState *ohci);
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static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev);
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/* Bitfields for the first word of an Endpoint Desciptor. */
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#define OHCI_ED_FA_SHIFT 0
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#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
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#define OHCI_ED_EN_SHIFT 7
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#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
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#define OHCI_ED_D_SHIFT 11
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#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
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#define OHCI_ED_S (1<<13)
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#define OHCI_ED_K (1<<14)
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#define OHCI_ED_F (1<<15)
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#define OHCI_ED_MPS_SHIFT 16
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#define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
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/* Flags in the head field of an Endpoint Desciptor. */
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#define OHCI_ED_H 1
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#define OHCI_ED_C 2
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/* Bitfields for the first word of a Transfer Desciptor. */
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#define OHCI_TD_R (1<<18)
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#define OHCI_TD_DP_SHIFT 19
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#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
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#define OHCI_TD_DI_SHIFT 21
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#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
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#define OHCI_TD_T0 (1<<24)
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#define OHCI_TD_T1 (1<<24)
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#define OHCI_TD_EC_SHIFT 26
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#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
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#define OHCI_TD_CC_SHIFT 28
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#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
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/* Bitfields for the first word of an Isochronous Transfer Desciptor. */
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/* CC & DI - same as in the General Transfer Desciptor */
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#define OHCI_TD_SF_SHIFT 0
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#define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
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#define OHCI_TD_FC_SHIFT 24
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#define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
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/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
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#define OHCI_TD_PSW_CC_SHIFT 12
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#define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
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#define OHCI_TD_PSW_SIZE_SHIFT 0
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#define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
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#define OHCI_PAGE_MASK 0xfffff000
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#define OHCI_OFFSET_MASK 0xfff
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#define OHCI_DPTR_MASK 0xfffffff0
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#define OHCI_BM(val, field) \
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(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
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#define OHCI_SET_BM(val, field, newval) do { \
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val &= ~OHCI_##field##_MASK; \
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val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
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} while(0)
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/* endpoint descriptor */
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struct ohci_ed {
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uint32_t flags;
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uint32_t tail;
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uint32_t head;
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uint32_t next;
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};
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/* General transfer descriptor */
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struct ohci_td {
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uint32_t flags;
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uint32_t cbp;
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uint32_t next;
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uint32_t be;
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};
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/* Isochronous transfer descriptor */
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struct ohci_iso_td {
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uint32_t flags;
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uint32_t bp;
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uint32_t next;
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uint32_t be;
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uint16_t offset[8];
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};
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#define USB_HZ 12000000
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/* OHCI Local stuff */
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#define OHCI_CTL_CBSR ((1<<0)|(1<<1))
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#define OHCI_CTL_PLE (1<<2)
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#define OHCI_CTL_IE (1<<3)
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#define OHCI_CTL_CLE (1<<4)
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#define OHCI_CTL_BLE (1<<5)
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#define OHCI_CTL_HCFS ((1<<6)|(1<<7))
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#define OHCI_USB_RESET 0x00
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#define OHCI_USB_RESUME 0x40
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#define OHCI_USB_OPERATIONAL 0x80
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#define OHCI_USB_SUSPEND 0xc0
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#define OHCI_CTL_IR (1<<8)
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#define OHCI_CTL_RWC (1<<9)
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#define OHCI_CTL_RWE (1<<10)
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#define OHCI_STATUS_HCR (1<<0)
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#define OHCI_STATUS_CLF (1<<1)
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#define OHCI_STATUS_BLF (1<<2)
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#define OHCI_STATUS_OCR (1<<3)
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#define OHCI_STATUS_SOC ((1<<6)|(1<<7))
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#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
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#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
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#define OHCI_INTR_SF (1<<2) /* Start of frame */
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#define OHCI_INTR_RD (1<<3) /* Resume detect */
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#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
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#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
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#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
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#define OHCI_INTR_OC (1<<30) /* Ownership change */
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#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
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#define OHCI_HCCA_SIZE 0x100
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#define OHCI_HCCA_MASK 0xffffff00
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#define OHCI_EDPTR_MASK 0xfffffff0
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#define OHCI_FMI_FI 0x00003fff
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#define OHCI_FMI_FSMPS 0xffff0000
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#define OHCI_FMI_FIT 0x80000000
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#define OHCI_FR_RT (1<<31)
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#define OHCI_LS_THRESH 0x628
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#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
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#define OHCI_RHA_PSM (1<<8)
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#define OHCI_RHA_NPS (1<<9)
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#define OHCI_RHA_DT (1<<10)
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#define OHCI_RHA_OCPM (1<<11)
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#define OHCI_RHA_NOCP (1<<12)
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#define OHCI_RHA_POTPGT_MASK 0xff000000
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#define OHCI_RHS_LPS (1<<0)
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#define OHCI_RHS_OCI (1<<1)
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#define OHCI_RHS_DRWE (1<<15)
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#define OHCI_RHS_LPSC (1<<16)
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#define OHCI_RHS_OCIC (1<<17)
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#define OHCI_RHS_CRWE (1<<31)
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#define OHCI_PORT_CCS (1<<0)
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#define OHCI_PORT_PES (1<<1)
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#define OHCI_PORT_PSS (1<<2)
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#define OHCI_PORT_POCI (1<<3)
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#define OHCI_PORT_PRS (1<<4)
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#define OHCI_PORT_PPS (1<<8)
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#define OHCI_PORT_LSDA (1<<9)
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#define OHCI_PORT_CSC (1<<16)
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#define OHCI_PORT_PESC (1<<17)
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#define OHCI_PORT_PSSC (1<<18)
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#define OHCI_PORT_OCIC (1<<19)
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#define OHCI_PORT_PRSC (1<<20)
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#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
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|OHCI_PORT_OCIC|OHCI_PORT_PRSC)
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#define OHCI_TD_DIR_SETUP 0x0
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#define OHCI_TD_DIR_OUT 0x1
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#define OHCI_TD_DIR_IN 0x2
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#define OHCI_TD_DIR_RESERVED 0x3
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#define OHCI_CC_NOERROR 0x0
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#define OHCI_CC_CRC 0x1
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#define OHCI_CC_BITSTUFFING 0x2
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#define OHCI_CC_DATATOGGLEMISMATCH 0x3
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#define OHCI_CC_STALL 0x4
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#define OHCI_CC_DEVICENOTRESPONDING 0x5
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#define OHCI_CC_PIDCHECKFAILURE 0x6
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#define OHCI_CC_UNDEXPETEDPID 0x7
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#define OHCI_CC_DATAOVERRUN 0x8
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#define OHCI_CC_DATAUNDERRUN 0x9
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#define OHCI_CC_BUFFEROVERRUN 0xc
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#define OHCI_CC_BUFFERUNDERRUN 0xd
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#define OHCI_HRESET_FSBIR (1 << 0)
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int64_t get_ticks_per_sec();
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int64_t get_clock();
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OHCIState *ohci_create(uint32_t base, int ports);
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uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr);
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void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val);
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void ohci_frame_boundary(void *opaque);
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int ohci_bus_start(OHCIState *ohci);
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void ohci_bus_stop(OHCIState *ohci);
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USBDevice *usb_hub_init(int nb_ports);
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USBDevice *usb_msd_init(const char *filename);
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USBDevice *eyetoy_init(void);
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USBDevice *usb_mouse_init(void);
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