mirror of https://github.com/PCSX2/pcsx2.git
660 lines
16 KiB
C
660 lines
16 KiB
C
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/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Arithmetic with immediate operand *
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* Format: OP rt, rs, immediate *
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*********************************************************/
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#ifndef ARITHMETICIMM_RECOMPILE
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REC_FUNC(ADDI);
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REC_FUNC(ADDIU);
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REC_FUNC(DADDI);
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REC_FUNC(DADDIU);
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REC_FUNC(ANDI);
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REC_FUNC(ORI);
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REC_FUNC(XORI);
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REC_FUNC(SLTI);
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REC_FUNC(SLTIU);
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#elif defined(EE_CONST_PROP)
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//// ADDI
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void recADDI_const( void )
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{
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].SL[0] + _Imm_;
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}
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void recADDI_(int info)
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{
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assert( !(info&PROCESS_EE_XMM) );
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EEINST_SETSIGNEXT(_Rt_);
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EEINST_SETSIGNEXT(_Rs_);
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if( info & PROCESS_EE_MMX ) {
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if( _Imm_ != 0 ) {
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u32* ptempmem = recAllocStackMem(4, 4);
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ptempmem[0] = _Imm_;
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if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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PADDDMtoR(EEREC_T, (u32)ptempmem);
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if( EEINST_ISLIVE1(_Rt_) ) _signExtendGPRtoMMX(EEREC_T, _Rt_, 0);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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else {
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// just move and sign extend
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if( !EEINST_HASLIVE1(_Rs_) ) {
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if( EEINST_ISLIVE1(_Rt_) )
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_signExtendGPRMMXtoMMX(EEREC_T, _Rt_, EEREC_S, _Rs_);
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else
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EEINST_RESETHASLIVE1(_Rt_);
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}
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else {
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if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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}
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}
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return;
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}
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if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) && (_Rt_ != _Rs_) ) {
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int rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE);
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SetMMXstate();
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if( _Imm_ != 0 ) {
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u32* ptempmem = recAllocStackMem(4, 4);
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ptempmem[0] = _Imm_;
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MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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PADDDMtoR(rtreg, (u32)ptempmem);
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if( EEINST_ISLIVE1(_Rt_) ) _signExtendGPRtoMMX(rtreg, _Rt_, 0);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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else {
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// just move and sign extend
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if( !EEINST_HASLIVE1(_Rs_) ) {
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MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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if( EEINST_ISLIVE1(_Rt_) ) _signExtendGPRtoMMX(rtreg, _Rt_, 0);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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else {
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MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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}
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}
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}
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else {
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if( _Rt_ == _Rs_ ) {
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ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
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if( EEINST_ISLIVE1(_Rt_) ) _signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if ( _Imm_ != 0 )
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ADD32ItoR( EAX, _Imm_ );
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if( EEINST_ISLIVE1(_Rt_) ) {
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CDQ( );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
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}
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else {
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EEINST_RESETHASLIVE1(_Rt_);
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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}
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}
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}
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}
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EERECOMPILE_CODEX(eeRecompileCode1, ADDI);
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////////////////////////////////////////////////////
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void recADDIU( void )
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{
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recADDI( );
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}
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////////////////////////////////////////////////////
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void recDADDI_const( void )
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{
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].SD[0] + _Imm_;
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}
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void recDADDI_(int info)
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{
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assert( !(info&PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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assert( cpucaps.hasStreamingSIMD2Extensions );
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if( _Imm_ != 0 ) {
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// flush
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u32* ptempmem = recAllocStackMem(8, 8);
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ptempmem[0] = _Imm_;
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ptempmem[1] = _Imm_ >= 0 ? 0 : 0xffffffff;
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if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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PADDQMtoR(EEREC_T, (u32)ptempmem);
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}
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else {
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if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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}
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return;
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}
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if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) && cpucaps.hasStreamingSIMD2Extensions ) {
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int rtreg;
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u32* ptempmem = recAllocStackMem(8, 8);
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ptempmem[0] = _Imm_;
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ptempmem[1] = _Imm_ >= 0 ? 0 : 0xffffffff;
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE);
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SetMMXstate();
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MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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PADDQMtoR(rtreg, (u32)ptempmem);
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}
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else {
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if( _Rt_ == _Rs_ ) {
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ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
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ADC32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], _Imm_<0?0xffffffff:0);
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if( EEINST_ISLIVE1(_Rt_) )
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MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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if ( _Imm_ != 0 )
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{
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ADD32ItoR( EAX, _Imm_ );
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if( EEINST_ISLIVE1(_Rt_) ) {
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ADC32ItoR( EDX, _Imm_ < 0?0xffffffff:0);
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}
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}
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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if( EEINST_ISLIVE1(_Rt_) )
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
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else
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EEINST_RESETHASLIVE1(_Rt_);
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}
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}
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}
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EERECOMPILE_CODEX(eeRecompileCode1, DADDI);
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//// DADDIU
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void recDADDIU( void )
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{
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recDADDI( );
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}
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//// SLTIU
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void recSLTIU_const()
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{
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] < (u64)(_Imm_);
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}
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extern void recSLTmemconstt(int regd, int regs, u32 mem, int sign);
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extern u32 s_sltone;
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void recSLTIU_(int info)
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{
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if( info & PROCESS_EE_MMX ) {
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if( EEINST_ISSIGNEXT(_Rs_) ) {
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u32* ptempmem = recAllocStackMem(8,4);
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ptempmem[0] = ((s32)(_Imm_))^0x80000000;
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ptempmem[1] = 0;
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recSLTmemconstt(EEREC_T, EEREC_S, (u32)ptempmem, 0);
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EEINST_SETSIGNEXT(_Rt_);
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return;
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}
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if( info & PROCESS_EE_MODEWRITES ) {
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MOVQRtoM((u32)&cpuRegs.GPR.r[_Rs_], EEREC_S);
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if( mmxregs[EEREC_S].reg == MMX_GPR+_Rs_ ) mmxregs[EEREC_S].mode &= ~MODE_WRITE;
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}
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mmxregs[EEREC_T].mode |= MODE_WRITE; // in case EEREC_T==EEREC_S
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}
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if( info & PROCESS_EE_MMX ) MOVDMtoMMX(EEREC_T, (u32)&s_sltone);
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else MOV32ItoR(EAX, 1);
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
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j8Ptr[0] = JB8( 0 );
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j8Ptr[2] = JA8( 0 );
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], (s32)_Imm_ );
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j8Ptr[1] = JB8(0);
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x86SetJ8(j8Ptr[2]);
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if( info & PROCESS_EE_MMX ) PXORRtoR(EEREC_T, EEREC_T);
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else XOR32RtoR(EAX, EAX);
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[1]);
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if( !(info & PROCESS_EE_MMX) ) {
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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if( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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EEINST_SETSIGNEXT(_Rt_);
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}
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EERECOMPILE_CODEX(eeRecompileCode1, SLTIU);
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//// SLTI
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void recSLTI_const()
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{
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].SD[0] < (s64)(_Imm_);
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}
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void recSLTI_(int info)
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{
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if( info & PROCESS_EE_MMX) {
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if( EEINST_ISSIGNEXT(_Rs_) ) {
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u32* ptempmem = recAllocStackMem(8,4);
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ptempmem[0] = _Imm_;
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ptempmem[1] = 0;
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recSLTmemconstt(EEREC_T, EEREC_S, (u32)ptempmem, 1);
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EEINST_SETSIGNEXT(_Rt_);
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return;
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}
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if( info & PROCESS_EE_MODEWRITES ) {
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MOVQRtoM((u32)&cpuRegs.GPR.r[_Rs_], EEREC_S);
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if( mmxregs[EEREC_S].reg == MMX_GPR+_Rs_ ) mmxregs[EEREC_S].mode &= ~MODE_WRITE;
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}
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mmxregs[EEREC_T].mode |= MODE_WRITE; // in case EEREC_T==EEREC_S
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}
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// test silent hill if modding
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if( info & PROCESS_EE_MMX ) MOVDMtoMMX(EEREC_T, (u32)&s_sltone);
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else MOV32ItoR(EAX, 1);
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
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j8Ptr[0] = JL8( 0 );
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j8Ptr[2] = JG8( 0 );
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], (s32)_Imm_ );
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j8Ptr[1] = JB8(0);
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x86SetJ8(j8Ptr[2]);
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if( info & PROCESS_EE_MMX ) PXORRtoR(EEREC_T, EEREC_T);
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else XOR32RtoR(EAX, EAX);
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[1]);
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if( !(info & PROCESS_EE_MMX) ) {
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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if( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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EEINST_SETSIGNEXT(_Rt_);
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}
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EERECOMPILE_CODEX(eeRecompileCode1, SLTI);
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||
|
|
|
||
|
|
//// ANDI
|
||
|
|
void recANDI_const()
|
||
|
|
{
|
||
|
|
g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] & (s64)_ImmU_;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op);
|
||
|
|
extern void LogicalOpMtoR(x86MMXRegType to, u32 from, int op);
|
||
|
|
extern void LogicalOp32RtoM(u32 to, x86IntRegType from, int op);
|
||
|
|
extern void LogicalOp32MtoR(x86IntRegType to, u32 from, int op);
|
||
|
|
extern void LogicalOp32ItoR(x86IntRegType to, u32 from, int op);
|
||
|
|
extern void LogicalOp32ItoM(u32 to, u32 from, int op);
|
||
|
|
|
||
|
|
void recLogicalOpI(int info, int op)
|
||
|
|
{
|
||
|
|
if( info & PROCESS_EE_MMX ) {
|
||
|
|
SetMMXstate();
|
||
|
|
|
||
|
|
if( _ImmU_ != 0 ) {
|
||
|
|
u32* ptempmem = recAllocStackMem(8, 8);
|
||
|
|
ptempmem[0] = _ImmU_;
|
||
|
|
ptempmem[1] = 0;
|
||
|
|
|
||
|
|
if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
|
||
|
|
LogicalOpMtoR(EEREC_T, (u32)ptempmem, op);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if( op == 0 ) PXORRtoR(EEREC_T, EEREC_T);
|
||
|
|
else {
|
||
|
|
if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) && ((_Rt_ != _Rs_) || (_ImmU_==0)) ) {
|
||
|
|
int rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE);
|
||
|
|
u32* ptempmem;
|
||
|
|
|
||
|
|
SetMMXstate();
|
||
|
|
|
||
|
|
ptempmem = recAllocStackMem(8, 8);
|
||
|
|
ptempmem[0] = _ImmU_;
|
||
|
|
ptempmem[1] = 0;
|
||
|
|
|
||
|
|
if( op == 0 ) {
|
||
|
|
if ( _ImmU_ != 0 ) {
|
||
|
|
if( _ImmU_ == 0xffff ) {
|
||
|
|
// take a shortcut
|
||
|
|
MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] - 2);
|
||
|
|
PSRLDItoR(rtreg, 16);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
||
|
|
PANDMtoR(rtreg, (u32)ptempmem);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else PXORRtoR(rtreg, rtreg);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
||
|
|
if ( _ImmU_ != 0 ) LogicalOpMtoR(rtreg, (u32)ptempmem, op);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if ( _ImmU_ != 0 )
|
||
|
|
{
|
||
|
|
if( _Rt_ == _Rs_ ) {
|
||
|
|
LogicalOp32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _ImmU_, op);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||
|
|
if( op != 0 && EEINST_ISLIVE1(_Rt_) )
|
||
|
|
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
||
|
|
LogicalOp32ItoR( EAX, _ImmU_, op);
|
||
|
|
if( op != 0 && EEINST_ISLIVE1(_Rt_) )
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
|
||
|
|
}
|
||
|
|
|
||
|
|
if( op == 0 ) {
|
||
|
|
if( EEINST_ISLIVE1(_Rt_ ) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
|
||
|
|
else EEINST_RESETHASLIVE1(_Rt_);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if( op == 0 ) {
|
||
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], 0 );
|
||
|
|
if( EEINST_ISLIVE1(_Rt_ ) )
|
||
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if( _Rt_ != _Rs_ ) {
|
||
|
|
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||
|
|
if( EEINST_ISLIVE1(_Rt_ ) )
|
||
|
|
MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
||
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
|
||
|
|
if( EEINST_ISLIVE1(_Rt_ ) )
|
||
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if( !EEINST_ISLIVE1(_Rt_) ) EEINST_RESETHASLIVE1(_Rt_);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void recANDI_(int info)
|
||
|
|
{
|
||
|
|
recLogicalOpI(info, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
EERECOMPILE_CODEX(eeRecompileCode1, ANDI);
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recORI_const()
|
||
|
|
{
|
||
|
|
g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] | (s64)_ImmU_;
|
||
|
|
}
|
||
|
|
|
||
|
|
void recORI_(int info)
|
||
|
|
{
|
||
|
|
recLogicalOpI(info, 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
EERECOMPILE_CODEX(eeRecompileCode1, ORI);
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recXORI_const()
|
||
|
|
{
|
||
|
|
g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] ^ (s64)_ImmU_;
|
||
|
|
}
|
||
|
|
|
||
|
|
void recXORI_(int info)
|
||
|
|
{
|
||
|
|
recLogicalOpI(info, 2);
|
||
|
|
}
|
||
|
|
|
||
|
|
EERECOMPILE_CODEX(eeRecompileCode1, XORI);
|
||
|
|
|
||
|
|
#else
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recADDI( void )
|
||
|
|
{
|
||
|
|
if ( ! _Rt_ )
|
||
|
|
{
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||
|
|
|
||
|
|
if ( _Imm_ != 0 )
|
||
|
|
{
|
||
|
|
ADD32ItoR( EAX, _Imm_ );
|
||
|
|
}
|
||
|
|
|
||
|
|
CDQ( );
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recADDIU( void )
|
||
|
|
{
|
||
|
|
recADDI( );
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recDADDI( void )
|
||
|
|
{
|
||
|
|
#ifdef __x86_64_
|
||
|
|
if ( ! _Rt_ )
|
||
|
|
{
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
MOV64MtoR( RAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||
|
|
if ( _Imm_ != 0 )
|
||
|
|
{
|
||
|
|
ADD64ItoR( EAX, _Imm_ );
|
||
|
|
}
|
||
|
|
MOV64RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], RAX );
|
||
|
|
#else
|
||
|
|
if ( ! _Rt_ )
|
||
|
|
{
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||
|
|
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
||
|
|
if ( _Imm_ != 0 )
|
||
|
|
{
|
||
|
|
ADD32ItoR( EAX, _Imm_ );
|
||
|
|
if ( _Imm_ < 0 )
|
||
|
|
{
|
||
|
|
ADC32ItoR( EDX, 0xffffffff );
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ADC32ItoR( EDX, 0 );
|
||
|
|
}
|
||
|
|
}
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recDADDIU( void )
|
||
|
|
{
|
||
|
|
recDADDI( );
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recSLTIU( void )
|
||
|
|
{
|
||
|
|
if ( ! _Rt_ )
|
||
|
|
return;
|
||
|
|
|
||
|
|
MOV32ItoR(EAX, 1);
|
||
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
|
||
|
|
j8Ptr[0] = JB8( 0 );
|
||
|
|
j8Ptr[2] = JA8( 0 );
|
||
|
|
|
||
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], (s32)_Imm_ );
|
||
|
|
j8Ptr[1] = JB8(0);
|
||
|
|
|
||
|
|
x86SetJ8(j8Ptr[2]);
|
||
|
|
XOR32RtoR(EAX, EAX);
|
||
|
|
|
||
|
|
x86SetJ8(j8Ptr[0]);
|
||
|
|
x86SetJ8(j8Ptr[1]);
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
|
||
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recSLTI( void )
|
||
|
|
{
|
||
|
|
if ( ! _Rt_ )
|
||
|
|
return;
|
||
|
|
|
||
|
|
// test silent hill if modding
|
||
|
|
MOV32ItoR(EAX, 1);
|
||
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
|
||
|
|
j8Ptr[0] = JL8( 0 );
|
||
|
|
j8Ptr[2] = JG8( 0 );
|
||
|
|
|
||
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], (s32)_Imm_ );
|
||
|
|
j8Ptr[1] = JB8(0);
|
||
|
|
|
||
|
|
x86SetJ8(j8Ptr[2]);
|
||
|
|
XOR32RtoR(EAX, EAX);
|
||
|
|
|
||
|
|
x86SetJ8(j8Ptr[0]);
|
||
|
|
x86SetJ8(j8Ptr[1]);
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
|
||
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recANDI( void )
|
||
|
|
{
|
||
|
|
if ( ! _Rt_ )
|
||
|
|
{
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
if ( _ImmU_ != 0 )
|
||
|
|
{
|
||
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||
|
|
AND32ItoR( EAX, _ImmU_ );
|
||
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
|
||
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
|
||
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], 0 );
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
static u64 _imm = 0; // temp immediate
|
||
|
|
|
||
|
|
void recORI( void )
|
||
|
|
{
|
||
|
|
if ( ! _Rt_ )
|
||
|
|
return;
|
||
|
|
|
||
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ] );
|
||
|
|
if ( _ImmU_ != 0 )
|
||
|
|
{
|
||
|
|
MOV32ItoM( (int)&_imm, _ImmU_ );
|
||
|
|
MOVQMtoR( MM1, (int)&_imm );
|
||
|
|
PORRtoR( MM0, MM1 );
|
||
|
|
}
|
||
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UD[ 0 ], MM0 );
|
||
|
|
SetMMXstate();
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////
|
||
|
|
void recXORI( void )
|
||
|
|
{
|
||
|
|
if ( ! _Rt_ )
|
||
|
|
return;
|
||
|
|
|
||
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ] );
|
||
|
|
if ( _ImmU_ != 0 )
|
||
|
|
{
|
||
|
|
MOV32ItoM( (int)&_imm, _ImmU_ );
|
||
|
|
MOVQMtoR( MM1, (int)&_imm );
|
||
|
|
PXORRtoR( MM0, MM1 );
|
||
|
|
}
|
||
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rt_ ], MM0 );
|
||
|
|
SetMMXstate();
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|