mirror of https://github.com/PCSX2/pcsx2.git
483 lines
14 KiB
C
483 lines
14 KiB
C
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/* Cpudetection lib
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if defined (__WIN32__)
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#include <windows.h>
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#endif
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#include <string.h>
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#include <stdio.h>
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#include "ix86.h"
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#if defined (__VCNET2005__)
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void __cpuid(int* CPUInfo, int InfoType);
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unsigned __int64 __rdtsc();
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#pragma intrinsic(__cpuid)
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#pragma intrinsic(__rdtsc)
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#endif
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CAPABILITIES cpucaps;
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CPUINFO cpuinfo;
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static s32 iCpuId( u32 cmd, u32 *regs )
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{
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int flag;
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#if defined (__VCNET2005__)
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__cpuid( regs, cmd );
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return 0;
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#elif defined (__MSCW32__) && !defined(__x86_64__)
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__asm
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{
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push ebx;
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push edi;
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pushfd;
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pop eax;
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mov edx, eax;
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xor eax, 1 << 21;
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push eax;
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popfd;
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pushfd;
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pop eax;
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xor eax, edx;
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mov flag, eax;
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}
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if ( ! flag )
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{
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return -1;
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}
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__asm
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{
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mov eax, cmd;
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cpuid;
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mov edi, [regs]
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mov [edi], eax;
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mov [edi+4], ebx;
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mov [edi+8], ecx;
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mov [edi+12], edx;
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pop edi;
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pop ebx;
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}
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return 0;
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#else
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__asm__ __volatile__ (
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#ifdef __x86_64__
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"sub $0x18, %%rsp\n"
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#endif
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"pushf\n"
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"pop %%eax\n"
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"mov %%eax, %%edx\n"
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"xor $0x200000, %%eax\n"
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"push %%eax\n"
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"popf\n"
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"pushf\n"
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"pop %%eax\n"
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"xor %%edx, %%eax\n"
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"mov %%eax, %0\n"
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#ifdef __x86_64__
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"add $0x18, %%rsp\n"
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#endif
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: "=r"(flag) :
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);
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if ( ! flag )
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{
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return -1;
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}
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__asm__ __volatile__ (
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"mov %4, %%eax\n"
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"cpuid\n"
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"mov %%eax, %0\n"
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"mov %%ebx, %1\n"
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"mov %%ecx, %2\n"
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"mov %%edx, %3\n"
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: "=m" (regs[0]), "=m" (regs[1]),
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"=m" (regs[2]), "=m" (regs[3])
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: "m"(cmd)
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: "eax", "ebx", "ecx", "edx"
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);
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return 0;
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#endif
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}
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u64 GetCPUTick( void )
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{
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#if defined (__VCNET2005__)
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return __rdtsc();
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#elif defined(__MSCW32__) && !defined(__x86_64__)
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__asm rdtsc;
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#else
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u32 _a, _d;
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__asm__ __volatile__ ("rdtsc" : "=a"(_a), "=d"(_d));
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return (u64)_a | ((u64)_d << 32);
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#endif
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}
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#if defined __LINUX__
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#include <sys/time.h>
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#include <errno.h>
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u32 timeGetTime( void )
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{
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struct timeval tv;
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gettimeofday( &tv, 0 );
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return tv.tv_sec * 1000 + tv.tv_usec / 1000;
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}
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#endif
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s64 CPUSpeedHz( unsigned int time )
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{
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s64 timeStart,
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timeStop;
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s64 startTick,
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endTick;
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s64 overhead;
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if( ! cpucaps.hasTimeStampCounter )
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{
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return 0; //check if function is supported
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}
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overhead = GetCPUTick() - GetCPUTick();
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timeStart = timeGetTime( );
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while( timeGetTime( ) == timeStart )
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{
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timeStart = timeGetTime( );
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}
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for(;;)
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{
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timeStop = timeGetTime( );
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if ( ( timeStop - timeStart ) > 1 )
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{
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startTick = GetCPUTick( );
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break;
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}
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}
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timeStart = timeStop;
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for(;;)
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{
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timeStop = timeGetTime( );
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if ( ( timeStop - timeStart ) > time )
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{
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endTick = GetCPUTick( );
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break;
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}
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}
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return (s64)( ( endTick - startTick ) + ( overhead ) );
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}
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////////////////////////////////////////////////////
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void cpudetectInit( void )
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{
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u32 regs[ 4 ];
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u32 cmds;
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u32 AMDspeed;
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s8 AMDspeedString[10];
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int cputype=0; // Cpu type
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//AMD 64 STUFF
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u32 x86_64_8BITBRANDID;
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u32 x86_64_12BITBRANDID;
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memset( cpuinfo.x86ID, 0, sizeof( cpuinfo.x86ID ) );
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cpuinfo.x86Family = 0;
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cpuinfo.x86Model = 0;
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cpuinfo.x86PType = 0;
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cpuinfo.x86StepID = 0;
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cpuinfo.x86Flags = 0;
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cpuinfo.x86EFlags = 0;
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if ( iCpuId( 0, regs ) == -1 ) return;
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cmds = regs[ 0 ];
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((u32*)cpuinfo.x86ID)[ 0 ] = regs[ 1 ];
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((u32*)cpuinfo.x86ID)[ 1 ] = regs[ 3 ];
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((u32*)cpuinfo.x86ID)[ 2 ] = regs[ 2 ];
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if ( cmds >= 0x00000001 )
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{
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if ( iCpuId( 0x00000001, regs ) != -1 )
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{
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cpuinfo.x86StepID = regs[ 0 ] & 0xf;
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cpuinfo.x86Model = (regs[ 0 ] >> 4) & 0xf;
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cpuinfo.x86Family = (regs[ 0 ] >> 8) & 0xf;
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cpuinfo.x86PType = (regs[ 0 ] >> 12) & 0x3;
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x86_64_8BITBRANDID = regs[1] & 0xff;
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cpuinfo.x86Flags = regs[ 3 ];
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}
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}
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if ( iCpuId( 0x80000000, regs ) != -1 )
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{
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cmds = regs[ 0 ];
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if ( cmds >= 0x80000001 )
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{
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if ( iCpuId( 0x80000001, regs ) != -1 )
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{
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x86_64_12BITBRANDID = regs[1] & 0xfff;
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cpuinfo.x86EFlags = regs[ 3 ];
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}
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}
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}
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switch(cpuinfo.x86PType)
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{
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case 0:
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strcpy( cpuinfo.x86Type, "Standard OEM");
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break;
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case 1:
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strcpy( cpuinfo.x86Type, "Overdrive");
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break;
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case 2:
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strcpy( cpuinfo.x86Type, "Dual");
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break;
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case 3:
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strcpy( cpuinfo.x86Type, "Reserved");
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break;
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default:
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strcpy( cpuinfo.x86Type, "Unknown");
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break;
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}
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if ( cpuinfo.x86ID[ 0 ] == 'G' ){ cputype=0;}//trick lines but if you know a way better ;p
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if ( cpuinfo.x86ID[ 0 ] == 'A' ){ cputype=1;}
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if ( cputype == 0 ) //intel cpu
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{
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if( ( cpuinfo.x86Family >= 7 ) && ( cpuinfo.x86Family < 15 ) )
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{
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strcpy( cpuinfo.x86Fam, "Intel P6 family (Not PIV and Higher then PPro" );
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}
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else
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{
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switch( cpuinfo.x86Family )
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{
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// Start at 486 because if it's below 486 there is no cpuid instruction
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case 4:
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strcpy( cpuinfo.x86Fam, "Intel 486" );
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break;
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case 5:
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switch( cpuinfo.x86Model )
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{
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case 4:
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case 8: // 0.25 <20>m
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strcpy( cpuinfo.x86Fam, "Intel Pentium (MMX)");
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break;
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default:
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strcpy( cpuinfo.x86Fam, "Intel Pentium" );
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}
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break;
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case 6:
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switch( cpuinfo.x86Model )
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{
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case 0: // Pentium pro (P6 A-Step)
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case 1: // Pentium pro
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strcpy( cpuinfo.x86Fam, "Intel Pentium Pro" );
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break;
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case 2: // 66 MHz FSB
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case 5: // Xeon/Celeron (0.25 <20>m)
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case 6: // Internal L2 cache
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strcpy( cpuinfo.x86Fam, "Intel Pentium II" );
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break;
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case 7: // Xeon external L2 cache
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case 8: // Xeon/Celeron with 256 KB on-die L2 cache
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case 10: // Xeon/Celeron with 1 or 2 MB on-die L2 cache
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case 11: // Xeon/Celeron with Tualatin core, on-die cache
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strcpy( cpuinfo.x86Fam, "Intel Pentium III" );
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break;
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default:
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strcpy( cpuinfo.x86Fam, "Intel Pentium Pro (Unknown)" );
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}
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break;
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case 15:
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switch( cpuinfo.x86Model )
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{
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case 0: // Willamette (A-Step)
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case 1: // Willamette
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strcpy( cpuinfo.x86Fam, "Willamette Intel Pentium IV" );
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break;
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case 2: // Northwood
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strcpy( cpuinfo.x86Fam, "Northwood Intel Pentium IV" );
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break;
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default:
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strcpy( cpuinfo.x86Fam, "Intel Pentium IV (Unknown)" );
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break;
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}
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break;
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default:
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strcpy( cpuinfo.x86Fam, "Unknown Intel CPU" );
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}
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}
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}
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else if ( cputype == 1 ) //AMD cpu
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{
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if( cpuinfo.x86Family >= 7 )
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{
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if((x86_64_12BITBRANDID !=0) || (x86_64_8BITBRANDID !=0))
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{
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if(x86_64_8BITBRANDID == 0 )
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{
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switch((x86_64_12BITBRANDID >>6)& 0x3f)
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{
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case 4:
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strcpy(cpuinfo.x86Fam,"AMD Athlon(tm) 64 Processor");
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AMDspeed = 22 + (x86_64_12BITBRANDID & 0x1f);
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//AMDspeedString = strtol(AMDspeed, (char**)NULL,10);
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sprintf(AMDspeedString," %d",AMDspeed);
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strcat(AMDspeedString,"00+");
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strcat(cpuinfo.x86Fam,AMDspeedString);
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break;
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case 12:
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strcpy(cpuinfo.x86Fam,"AMD Opteron(tm) Processor");
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break;
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default:
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strcpy(cpuinfo.x86Fam,"Unknown AMD 64 proccesor");
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}
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|||
|
|
}
|
|||
|
|
else //8bit brand id is non zero
|
|||
|
|
{
|
|||
|
|
strcpy(cpuinfo.x86Fam,"Unsupported yet AMD64 cpu");
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
strcpy( cpuinfo.x86Fam, "AMD K7+" );
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
switch ( cpuinfo.x86Family )
|
|||
|
|
{
|
|||
|
|
case 4:
|
|||
|
|
switch( cpuinfo.x86Model )
|
|||
|
|
{
|
|||
|
|
case 14:
|
|||
|
|
case 15: // Write-back enhanced
|
|||
|
|
strcpy( cpuinfo.x86Fam, "AMD 5x86" );
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case 3: // DX2
|
|||
|
|
case 7: // Write-back enhanced DX2
|
|||
|
|
case 8: // DX4
|
|||
|
|
case 9: // Write-back enhanced DX4
|
|||
|
|
strcpy( cpuinfo.x86Fam, "AMD 486" );
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
default:
|
|||
|
|
strcpy( cpuinfo.x86Fam, "AMD Unknown" );
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case 5:
|
|||
|
|
switch( cpuinfo.x86Model)
|
|||
|
|
{
|
|||
|
|
case 0: // SSA 5 (75, 90 and 100 Mhz)
|
|||
|
|
case 1: // 5k86 (PR 120 and 133 MHz)
|
|||
|
|
case 2: // 5k86 (PR 166 MHz)
|
|||
|
|
case 3: // K5 5k86 (PR 200 MHz)
|
|||
|
|
strcpy( cpuinfo.x86Fam, "AMD K5" );
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case 6:
|
|||
|
|
case 7: // (0.25 <20>m)
|
|||
|
|
case 8: // K6-2
|
|||
|
|
case 9: // K6-III
|
|||
|
|
case 14: // K6-2+ / K6-III+
|
|||
|
|
strcpy( cpuinfo.x86Fam, "AMD K6" );
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
default:
|
|||
|
|
strcpy( cpuinfo.x86Fam, "AMD Unknown" );
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
case 6:
|
|||
|
|
strcpy( cpuinfo.x86Fam, "AMD K7" );
|
|||
|
|
break;
|
|||
|
|
default:
|
|||
|
|
strcpy( cpuinfo.x86Fam, "Unknown AMD CPU" );
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
//capabilities
|
|||
|
|
cpucaps.hasFloatingPointUnit = ( cpuinfo.x86Flags >> 0 ) & 1;
|
|||
|
|
cpucaps.hasVirtual8086ModeEnhancements = ( cpuinfo.x86Flags >> 1 ) & 1;
|
|||
|
|
cpucaps.hasDebuggingExtensions = ( cpuinfo.x86Flags >> 2 ) & 1;
|
|||
|
|
cpucaps.hasPageSizeExtensions = ( cpuinfo.x86Flags >> 3 ) & 1;
|
|||
|
|
cpucaps.hasTimeStampCounter = ( cpuinfo.x86Flags >> 4 ) & 1;
|
|||
|
|
cpucaps.hasModelSpecificRegisters = ( cpuinfo.x86Flags >> 5 ) & 1;
|
|||
|
|
cpucaps.hasPhysicalAddressExtension = ( cpuinfo.x86Flags >> 6 ) & 1;
|
|||
|
|
cpucaps.hasMachineCheckArchitecture = ( cpuinfo.x86Flags >> 7 ) & 1;
|
|||
|
|
cpucaps.hasCOMPXCHG8BInstruction = ( cpuinfo.x86Flags >> 8 ) & 1;
|
|||
|
|
cpucaps.hasAdvancedProgrammableInterruptController = ( cpuinfo.x86Flags >> 9 ) & 1;
|
|||
|
|
cpucaps.hasSEPFastSystemCall = ( cpuinfo.x86Flags >> 11 ) & 1;
|
|||
|
|
cpucaps.hasMemoryTypeRangeRegisters = ( cpuinfo.x86Flags >> 12 ) & 1;
|
|||
|
|
cpucaps.hasPTEGlobalFlag = ( cpuinfo.x86Flags >> 13 ) & 1;
|
|||
|
|
cpucaps.hasMachineCheckArchitecture = ( cpuinfo.x86Flags >> 14 ) & 1;
|
|||
|
|
cpucaps.hasConditionalMoveAndCompareInstructions = ( cpuinfo.x86Flags >> 15 ) & 1;
|
|||
|
|
cpucaps.hasFGPageAttributeTable = ( cpuinfo.x86Flags >> 16 ) & 1;
|
|||
|
|
cpucaps.has36bitPageSizeExtension = ( cpuinfo.x86Flags >> 17 ) & 1;
|
|||
|
|
cpucaps.hasProcessorSerialNumber = ( cpuinfo.x86Flags >> 18 ) & 1;
|
|||
|
|
cpucaps.hasCFLUSHInstruction = ( cpuinfo.x86Flags >> 19 ) & 1;
|
|||
|
|
cpucaps.hasDebugStore = ( cpuinfo.x86Flags >> 21 ) & 1;
|
|||
|
|
cpucaps.hasACPIThermalMonitorAndClockControl = ( cpuinfo.x86Flags >> 22 ) & 1;
|
|||
|
|
cpucaps.hasMultimediaExtensions = ( cpuinfo.x86Flags >> 23 ) & 1; //mmx
|
|||
|
|
cpucaps.hasFastStreamingSIMDExtensionsSaveRestore = ( cpuinfo.x86Flags >> 24 ) & 1;
|
|||
|
|
cpucaps.hasStreamingSIMDExtensions = ( cpuinfo.x86Flags >> 25 ) & 1; //sse
|
|||
|
|
cpucaps.hasStreamingSIMD2Extensions = ( cpuinfo.x86Flags >> 26 ) & 1; //sse2
|
|||
|
|
cpucaps.hasSelfSnoop = ( cpuinfo.x86Flags >> 27 ) & 1;
|
|||
|
|
cpucaps.hasHyperThreading = ( cpuinfo.x86Flags >> 28 ) & 1;
|
|||
|
|
cpucaps.hasThermalMonitor = ( cpuinfo.x86Flags >> 29 ) & 1;
|
|||
|
|
cpucaps.hasIntel64BitArchitecture = ( cpuinfo.x86Flags >> 30 ) & 1;
|
|||
|
|
//that is only for AMDs
|
|||
|
|
cpucaps.hasMultimediaExtensionsExt = ( cpuinfo.x86EFlags >> 22 ) & 1; //mmx2
|
|||
|
|
cpucaps.hasAMD64BitArchitecture = ( cpuinfo.x86EFlags >> 29 ) & 1; //64bit cpu
|
|||
|
|
cpucaps.has3DNOWInstructionExtensionsExt = ( cpuinfo.x86EFlags >> 30 ) & 1; //3dnow+
|
|||
|
|
cpucaps.has3DNOWInstructionExtensions = ( cpuinfo.x86EFlags >> 31 ) & 1; //3dnow
|
|||
|
|
cpuinfo.cpuspeed = (u32 )(CPUSpeedHz( 1000 ) / 1000000);
|
|||
|
|
}
|