diff --git a/include/asmfunc.h b/include/asm_macros.h
similarity index 69%
rename from include/asmfunc.h
rename to include/asm_macros.h
index 0c528f0..d5a8e85 100644
--- a/include/asmfunc.h
+++ b/include/asm_macros.h
@@ -23,10 +23,24 @@
#endif
-.macro ASM_FUNC name
- .section .text.\name, "ax", %progbits
- .global \name
- .type \name %function
- .align 2
+.macro BEGIN_ASM_FUNC name, type=arm, linkage=global, section=text
+ .section .\section\().\name, "ax", %progbits
+.if \type == thumb
+ .align 1
+ .thumb
+.else
+ .align 2
+ .arm
+.endif
+ .\linkage \name
+ .type \name, %function
+ .func \name
+ .cfi_sections .debug_frame
+ .cfi_startproc
\name:
.endm
+
+.macro END_ASM_FUNC
+ .cfi_endproc
+ .endfunc
+.endm
diff --git a/source/arm11/hardware/cache.s b/source/arm11/hardware/cache.s
index e8cff85..87515a1 100644
--- a/source/arm11/hardware/cache.s
+++ b/source/arm11/hardware/cache.s
@@ -16,9 +16,8 @@
* along with this program. If not, see .
*/
-#include "asmfunc.h"
+#include "asm_macros.h"
-.arm
.cpu mpcore
.fpu vfpv2
@@ -29,16 +28,17 @@
-ASM_FUNC invalidateICache
+BEGIN_ASM_FUNC invalidateICache
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ Invalidate Entire Instruction Cache, also flushes the branch target cache
@mcr p15, 0, r0, c7, c5, 6 @ Flush Entire Branch Target Cache
mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer
bx lr
+END_ASM_FUNC
-ASM_FUNC invalidateICacheRange
+BEGIN_ASM_FUNC invalidateICacheRange
add r1, r1, r0
bic r0, r0, #(CACHE_LINE_SIZE - 1)
mov r2, #0
@@ -51,23 +51,26 @@ ASM_FUNC invalidateICacheRange
mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
mcr p15, 0, r2, c7, c5, 4 @ Flush Prefetch Buffer
bx lr
+END_ASM_FUNC
-ASM_FUNC flushDCache
+BEGIN_ASM_FUNC flushDCache
mov r0, #0
mcr p15, 0, r0, c7, c10, 0 @ "Clean Entire Data Cache"
mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
bx lr
+END_ASM_FUNC
-ASM_FUNC flushInvalidateDCache
+BEGIN_ASM_FUNC flushInvalidateDCache
mov r0, #0
mcr p15, 0, r0, c7, c14, 0 @ "Clean and Invalidate Entire Data Cache"
mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
bx lr
+END_ASM_FUNC
-ASM_FUNC flushDCacheRange
+BEGIN_ASM_FUNC flushDCacheRange
cmp r1, #DCACHE_SIZE
bhi flushDCache
add r1, r1, r0
@@ -80,9 +83,10 @@ ASM_FUNC flushDCacheRange
blt flushDCacheRange_lp
mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
bx lr
+END_ASM_FUNC
-ASM_FUNC flushInvalidateDCacheRange
+BEGIN_ASM_FUNC flushInvalidateDCacheRange
cmp r1, #DCACHE_SIZE
bhi flushInvalidateDCache
add r1, r1, r0
@@ -95,16 +99,18 @@ ASM_FUNC flushInvalidateDCacheRange
blt flushInvalidateDCacheRange_lp
mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
bx lr
+END_ASM_FUNC
-ASM_FUNC invalidateDCache
+BEGIN_ASM_FUNC invalidateDCache
mov r0, #0
mcr p15, 0, r0, c7, c6, 0 @ Invalidate Entire Data Cache
mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
bx lr
+END_ASM_FUNC
-ASM_FUNC invalidateDCacheRange
+BEGIN_ASM_FUNC invalidateDCacheRange
cmp r1, #DCACHE_SIZE
bhi flushInvalidateDCache
add r1, r1, r0
@@ -121,6 +127,4 @@ ASM_FUNC invalidateDCacheRange
blt invalidateDCacheRange_lp
mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
bx lr
-
-
-.pool
+END_ASM_FUNC
diff --git a/source/arm11/hardware/exception.s b/source/arm11/hardware/exception.s
index 6797d8f..12480f8 100644
--- a/source/arm11/hardware/exception.s
+++ b/source/arm11/hardware/exception.s
@@ -16,29 +16,26 @@
* along with this program. If not, see .
*/
+#include "asm_macros.h"
#include "arm.h"
-#include "asmfunc.h"
#include "mem_map.h"
-.arm
.cpu mpcore
.fpu vfpv2
-.extern deinitCpu
-.extern guruMeditation
-.extern irqIsrTable
-
-
-
-ASM_FUNC undefInstrHandler
- msr cpsr_f, #0<<29 @ Abuse conditional flags in cpsr for temporary exception type storage
+.macro EXCEPTION_ENTRY name, type
+BEGIN_ASM_FUNC \name
+ msr cpsr_f, #\type @ Abuse conditional flags in cpsr for temporary exception type storage
b exceptionHandler
-ASM_FUNC prefetchAbortHandler
- msr cpsr_f, #1<<29
- b exceptionHandler
-ASM_FUNC dataAbortHandler
- msr cpsr_f, #2<<29
-ASM_FUNC exceptionHandler
+END_ASM_FUNC
+.endm
+
+
+
+EXCEPTION_ENTRY undefInstrHandler, 0<<29
+EXCEPTION_ENTRY prefetchAbortHandler, 1<<29
+EXCEPTION_ENTRY dataAbortHandler, 2<<29
+BEGIN_ASM_FUNC exceptionHandler
sub sp, #68
stmia sp, {r0-r14}^ @ Save all user/system mode regs except pc
mrs r2, spsr @ Get saved cpsr
@@ -61,9 +58,10 @@ exceptionHandler_skip_other_mode:
mov sp, r5
mov r1, r5
b guruMeditation @ r0 = exception type, r1 = reg dump ptr {r0-r14, pc (unmodified), cpsr}
+END_ASM_FUNC
-ASM_FUNC irqHandler
+BEGIN_ASM_FUNC irqHandler
sub lr, lr, #4
srsfd sp!, #PSR_SYS_MODE @ Store lr and spsr on system mode stack
cps #PSR_SYS_MODE
@@ -90,6 +88,4 @@ irqHandler_skip_processing:
str r0, [r12, #0x110] @ REG_CPU_II_EOI
ldmfd sp!, {r0-r3, r12, lr}
rfefd sp! @ Restore lr (pc) and spsr (cpsr)
-
-
-.pool
+END_ASM_FUNC
diff --git a/source/arm11/start.s b/source/arm11/start.s
index 7d13f6d..938a572 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -17,49 +17,37 @@
*/
#include "arm.h"
-#define ARM9
#include "mem_map.h"
-#undef ARM9
-.arm
.cpu mpcore
.fpu vfpv2
-.global _start
-.global _init
-.global deinitCpu
+.macro BEGIN_ASM_FUNC name, type=arm, linkage=global
+.if \type == thumb
+ .align 1
+ .thumb
+.else
+ .align 2
+ .arm
+.endif
+ .\linkage \name
+ .type \name, %function
+ .func \name
+ .cfi_sections .debug_frame
+ .cfi_startproc
+\name:
+.endm
-.type vectors %function
-.type _start %function
-.type stubExceptionVectors %function
-.type setupVfp %function
-.type _init %function
-.type deinitCpu %function
+.macro END_ASM_FUNC
+ .cfi_endproc
+ .endfunc
+.endm
-.extern irqHandler
-.extern undefInstrHandler
-.extern prefetchAbortHandler
-.extern dataAbortHandler
-.extern __bss_start__
-.extern __bss_end__
-.extern __end__
-.extern iomemset
-.extern iomemcpy
-.extern fake_heap_start
-.extern fake_heap_end
-.extern setupMmu
-.extern __libc_init_array
-.extern core123Init
-.extern __systemInit
-.extern main
-.extern __systemDeinit
-
-.section ".crt0", "ax"
+.section .crt0, "ax", %progbits
-__start__:
-vectors:
+BEGIN_ASM_FUNC vectors
ldr pc, resetHandlerPtr @ Reset vector
ldr pc, undefInstrHandlerPtr @ Undefined instruction vector
udf #3 @ Software interrupt (SVC) vector
@@ -68,16 +56,17 @@ vectors:
udf #6 @ Reserved (unused) vector
ldr pc, irqHandlerPtr @ Interrupt (IRQ) vector
udf #8 @ Fast interrupt (FIQ) vector
- resetHandlerPtr: .word _start
- undefInstrHandlerPtr: .word undefInstrHandler
- @svcHandlerPtr: .word (vectors + 0x08)
- prefetchAbortHandlerPtr: .word prefetchAbortHandler
- dataAbortHandlerPtr: .word dataAbortHandler
- irqHandlerPtr: .word irqHandler
- @fiqHandlerPtr: .word (vectors + 0x1C)
+ resetHandlerPtr: .4byte _start
+ undefInstrHandlerPtr: .4byte undefInstrHandler
+ @svcHandlerPtr: .4byte (vectors + 0x08)
+ prefetchAbortHandlerPtr: .4byte prefetchAbortHandler
+ dataAbortHandlerPtr: .4byte dataAbortHandler
+ irqHandlerPtr: .4byte irqHandler
+ @fiqHandlerPtr: .4byte (vectors + 0x1C)
+END_ASM_FUNC
-_start:
+BEGIN_ASM_FUNC _start
cpsid aif, #PSR_SVC_MODE
@ Control register:
@@ -155,18 +144,18 @@ _start_lp:
.pool
_sysmode_stacks:
- .word A11_C0_STACK_END @ Stack for core 0
- .word A11_C1_STACK_END @ Stack for core 1
- .word A11_C2_STACK_END @ Stack for core 2
- .word A11_C3_STACK_END @ Stack for core 3
+ .4byte A11_C0_STACK_END @ Stack for core 0
+ .4byte A11_C1_STACK_END @ Stack for core 1
+ .4byte A11_C2_STACK_END @ Stack for core 2
+ .4byte A11_C3_STACK_END @ Stack for core 3
_dummyArgv:
- .word 0
+ .4byte 0
+END_ASM_FUNC
#define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF))
-.align 2
-stubExceptionVectors:
+BEGIN_ASM_FUNC stubExceptionVectors
ldr r0, =A11_VECTORS_START
ldr r2, =MAKE_BRANCH(0, 0) @ Endless loop
mov r1, #6
@@ -177,10 +166,10 @@ stubExceptionVectors:
bx lr
.pool
+END_ASM_FUNC
-.align 2
-setupVfp:
+BEGIN_ASM_FUNC setupVfp
mov r0, #0xF00000 @ Give full access to cp10/11 in user and privileged mode
mov r1, #0
mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register
@@ -190,19 +179,15 @@ setupVfp:
fmxr fpexc, r0 @ Write Floating-point exception register
fmxr fpscr, r1 @ Write Floating-Point Status and Control Register
bx lr
-
-.pool
+END_ASM_FUNC
-.align 2
-_init:
+BEGIN_ASM_FUNC _init, thumb
bx lr
-
-.pool
+END_ASM_FUNC
-.align 2
-deinitCpu:
+BEGIN_ASM_FUNC deinitCpu
mov r3, lr
cpsid aif, #PSR_SYS_MODE
@@ -226,3 +211,4 @@ deinitCpu:
bx r3
.pool
+END_ASM_FUNC
diff --git a/source/arm9/arm7_stub.s b/source/arm9/arm7_stub.s
index 4645e3d..89cf523 100644
--- a/source/arm9/arm7_stub.s
+++ b/source/arm9/arm7_stub.s
@@ -1,17 +1,12 @@
-.arm
+#include "asm_macros.h"
+
.cpu arm7tdmi
.fpu softvfp
-.global _arm7_stub_start
-.global _arm7_stub_swi
-.global _arm7_stub_end
-
-.type _arm7_stub_start %function
-.align 2
@ Must be located at 0x3007E00.
-_arm7_stub_start:
+BEGIN_ASM_FUNC _arm7_stub_start
mov r0, #0xD3
adr r1, _arm7_stub_start + 0x200 @ 0x3008000
msr CPSR_cxsf, r0
@@ -41,13 +36,17 @@ wait_vcount_160_lp:
mov r4, r3 @ Needed for function call 0xBC below.
mov r0, #0xFF
+
+.global _arm7_stub_swi
_arm7_stub_swi:
swi 0x10 @ RegisterRamReset
@swi 0x26 @ HardReset (BIOS animation)
mov r0, #0xBC
mov r2, #0
bx r0
-.pool
+.pool
.align 2
+.global _arm7_stub_end
_arm7_stub_end:
+END_ASM_FUNC
diff --git a/source/arm9/hardware/cache.s b/source/arm9/hardware/cache.s
index 19b81ff..8266651 100644
--- a/source/arm9/hardware/cache.s
+++ b/source/arm9/hardware/cache.s
@@ -16,9 +16,8 @@
* along with this program. If not, see .
*/
-#include "asmfunc.h"
+#include "asm_macros.h"
-.arm
.cpu arm946e-s
.fpu softvfp
@@ -29,13 +28,14 @@
-ASM_FUNC invalidateICache
+BEGIN_ASM_FUNC invalidateICache
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ "Flush instruction cache"
bx lr
+END_ASM_FUNC
-ASM_FUNC invalidateICacheRange
+BEGIN_ASM_FUNC invalidateICacheRange
add r1, r1, r0
bic r0, r0, #(CACHE_LINE_SIZE - 1)
invalidateICacheRange_lp:
@@ -44,9 +44,10 @@ ASM_FUNC invalidateICacheRange
cmp r0, r1
blt invalidateICacheRange_lp
bx lr
+END_ASM_FUNC
-ASM_FUNC flushDCache
+BEGIN_ASM_FUNC flushDCache
mov r1, #0
flushDCache_outer_lp:
mov r0, #0
@@ -61,9 +62,10 @@ ASM_FUNC flushDCache
bne flushDCache_outer_lp
mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer
bx lr
+END_ASM_FUNC
-ASM_FUNC flushInvalidateDCache
+BEGIN_ASM_FUNC flushInvalidateDCache
mov r1, #0
flushInvalidateDCache_outer_lp:
mov r0, #0
@@ -78,9 +80,10 @@ ASM_FUNC flushInvalidateDCache
bne flushInvalidateDCache_outer_lp
mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer
bx lr
+END_ASM_FUNC
-ASM_FUNC flushDCacheRange
+BEGIN_ASM_FUNC flushDCacheRange
cmp r1, #DCACHE_SIZE
bhi flushDCache
add r1, r1, r0
@@ -93,9 +96,10 @@ ASM_FUNC flushDCacheRange
blt flushDCacheRange_lp
mcr p15, 0, r2, c7, c10, 4 @ Drain write buffer
bx lr
+END_ASM_FUNC
-ASM_FUNC flushInvalidateDCacheRange
+BEGIN_ASM_FUNC flushInvalidateDCacheRange
cmp r1, #DCACHE_SIZE
bhi flushInvalidateDCache
add r1, r1, r0
@@ -108,15 +112,17 @@ ASM_FUNC flushInvalidateDCacheRange
blt flushInvalidateDCacheRange_lp
mcr p15, 0, r2, c7, c10, 4 @ Drain write buffer
bx lr
+END_ASM_FUNC
-ASM_FUNC invalidateDCache
+BEGIN_ASM_FUNC invalidateDCache
mov r0, #0
mcr p15, 0, r0, c7, c6, 0 @ "Flush data cache"
bx lr
+END_ASM_FUNC
-ASM_FUNC invalidateDCacheRange
+BEGIN_ASM_FUNC invalidateDCacheRange
cmp r1, #DCACHE_SIZE
bhi flushInvalidateDCache
add r1, r1, r0
@@ -133,6 +139,4 @@ ASM_FUNC invalidateDCacheRange
blt invalidateDCacheRange_lp
mcr p15, 0, r2, c7, c10, 4 @ Drain write buffer
bx lr
-
-
-.pool
+END_ASM_FUNC
diff --git a/source/arm9/hardware/exception.s b/source/arm9/hardware/exception.s
index dc7a1dc..305d9f2 100644
--- a/source/arm9/hardware/exception.s
+++ b/source/arm9/hardware/exception.s
@@ -16,29 +16,26 @@
* along with this program. If not, see .
*/
+#include "asm_macros.h"
#include "arm.h"
-#include "asmfunc.h"
#include "mem_map.h"
-.arm
.cpu arm946e-s
.fpu softvfp
-.extern deinitCpu
-.extern guruMeditation
-.extern irqIsrTable
-
-
-
-ASM_FUNC undefInstrHandler
- msr cpsr_f, #0<<29 @ Abuse conditional flags in cpsr for temporary exception type storage
+.macro EXCEPTION_ENTRY name, type
+BEGIN_ASM_FUNC \name
+ msr cpsr_f, #\type @ Abuse conditional flags in cpsr for temporary exception type storage
b exceptionHandler
-ASM_FUNC prefetchAbortHandler
- msr cpsr_f, #1<<29
- b exceptionHandler
-ASM_FUNC dataAbortHandler
- msr cpsr_f, #2<<29
-ASM_FUNC exceptionHandler
+END_ASM_FUNC
+.endm
+
+
+
+EXCEPTION_ENTRY undefInstrHandler, 0<<29
+EXCEPTION_ENTRY prefetchAbortHandler, 1<<29
+EXCEPTION_ENTRY dataAbortHandler, 2<<29
+BEGIN_ASM_FUNC exceptionHandler
sub sp, #68
stmia sp, {r0-r14}^ @ Save all user/system mode regs except pc
mrs r2, spsr @ Get saved cpsr
@@ -61,9 +58,10 @@ exceptionHandler_skip_other_mode:
mov sp, r5
mov r1, r5
b guruMeditation @ r0 = exception type, r1 = reg dump ptr {r0-r14, pc (unmodified), cpsr}
+END_ASM_FUNC
-ASM_FUNC irqHandler
+BEGIN_ASM_FUNC irqHandler
sub lr, lr, #4
stmfd sp!, {r0-r3, r12, lr}
ldr r12, =IO_MEM_ARM9_ONLY + 0x1000 @ REG_IRQ_IE
@@ -92,6 +90,4 @@ ASM_FUNC irqHandler
msr spsr_cxsf, r0
irqHandler_skip_processing:
ldmfd sp!, {r0-r3, r12, pc}^
-
-
-.pool
+END_ASM_FUNC
diff --git a/source/arm9/start.s b/source/arm9/start.s
index a7d877a..dc6975b 100644
--- a/source/arm9/start.s
+++ b/source/arm9/start.s
@@ -17,47 +17,37 @@
*/
#include "arm.h"
-#define ARM11
#include "mem_map.h"
-#undef ARM11
-.arm
.cpu arm946e-s
.fpu softvfp
-.global _start
-.global _init
-.global deinitCpu
+.macro BEGIN_ASM_FUNC name, type=arm, linkage=global
+.if \type == thumb
+ .align 1
+ .thumb
+.else
+ .align 2
+ .arm
+.endif
+ .\linkage \name
+ .type \name, %function
+ .func \name
+ .cfi_sections .debug_frame
+ .cfi_startproc
+\name:
+.endm
-.type _start %function
-.type setupExceptionVectors %function
-.type setupTcms %function
-.type setupMpu %function
-.type _init %function
-.type deinitCpu %function
+.macro END_ASM_FUNC
+ .cfi_endproc
+ .endfunc
+.endm
-.extern __bss_start__
-.extern __bss_end__
-.extern __end__
-.extern iomemset
-.extern iomemcpy
-.extern fake_heap_start
-.extern fake_heap_end
-.extern __libc_init_array
-.extern __systemInit
-.extern main
-.extern __systemDeinit
-.extern irqHandler
-.extern undefInstrHandler
-.extern prefetchAbortHandler
-.extern dataAbortHandler
-
-.section ".crt0", "ax"
+.section .crt0, "ax", %progbits
-__start__:
-_start:
+BEGIN_ASM_FUNC _start
msr cpsr_cxsf, #PSR_INT_OFF | PSR_SVC_MODE
@ Control register:
@@ -125,13 +115,13 @@ _start:
.pool
_dummyArgv:
- .word 0
+ .4byte 0
+END_ASM_FUNC
#define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF))
-.align 2
-setupExceptionVectors:
+BEGIN_ASM_FUNC setupExceptionVectors
adr r0, _vectorStubs
ldr r1, =A9_VECTORS_START
ldmia r0!, {r2-r9}
@@ -143,21 +133,21 @@ setupExceptionVectors:
.pool
_vectorStubs:
ldr pc, irqHandlerPtr
- irqHandlerPtr: .word irqHandler
+ irqHandlerPtr: .4byte irqHandler
udf #2
- fiqHandlerPtr: .word (A9_VECTORS_START + 0x08)
+ fiqHandlerPtr: .4byte (A9_VECTORS_START + 0x08)
udf #3
- svcHandlerPtr: .word (A9_VECTORS_START + 0x10)
+ svcHandlerPtr: .4byte (A9_VECTORS_START + 0x10)
ldr pc, undefInstrHandlerPtr
- undefInstrHandlerPtr: .word undefInstrHandler
+ undefInstrHandlerPtr: .4byte undefInstrHandler
ldr pc, prefetchAbortHandlerPtr
- prefetchAbortHandlerPtr: .word prefetchAbortHandler
+ prefetchAbortHandlerPtr: .4byte prefetchAbortHandler
ldr pc, dataAbortHandlerPtr
- dataAbortHandlerPtr: .word dataAbortHandler
+ dataAbortHandlerPtr: .4byte dataAbortHandler
+END_ASM_FUNC
-.align 2
-setupTcms:
+BEGIN_ASM_FUNC setupTcms
ldr r1, =(ITCM_BASE | 0x24) @ Base = 0x00000000, size = 128 MiB (32 KiB mirrored)
ldr r0, =(DTCM_BASE | 0x0A) @ Base = 0xFFF00000, size = 16 KiB
mcr p15, 0, r0, c9, c1, 0 @ Write DTCM region reg
@@ -168,6 +158,7 @@ setupTcms:
bx lr
.pool
+END_ASM_FUNC
#define REGION_4KiB (0b01011)
@@ -202,8 +193,7 @@ setupTcms:
#define MAKE_PERMISSIONS(r0, r1, r2, r3, r4, r5, r6, r7) \
((r0) | (r1<<4) | (r2<<8) | (r3<<12) | (r4<<16) | (r5<<20) | (r6<<24) | (r7<<28))
-.align 2
-setupMpu:
+BEGIN_ASM_FUNC setupMpu
adr r0, _mpu_regions @ Table at end of file
ldm r0, {r1-r10}
mcr p15, 0, r1, c6, c0, 0 @ Write MPU region reg 0-7
@@ -260,6 +250,7 @@ setupMpu:
mcr p15, 0, r0, c1, c0, 0 @ Write control register
bx lr
+.pool
_mpu_regions:
@ Region 0: ITCM kernel mirror 32 KiB
@ Region 1: ARM9 internal mem + N3DS extension 2 MiB
@@ -269,14 +260,14 @@ _mpu_regions:
@ Region 5: FCRAM + N3DS extension 256 MiB
@ Region 6: DTCM 16 KiB
@ Region 7: Exception vectors + ARM9 bootrom 64 KiB
- .word MAKE_REGION(ITCM_KERNEL_MIRROR, REGION_32KiB)
- .word MAKE_REGION(A9_RAM_BASE, REGION_2MiB)
- .word MAKE_REGION(IO_MEM_ARM9_ONLY, REGION_2MiB)
- .word MAKE_REGION(VRAM_BASE, REGION_8MiB)
- .word MAKE_REGION(DSP_MEM_BASE, REGION_1MiB)
- .word MAKE_REGION(FCRAM_BASE, REGION_256MiB)
- .word MAKE_REGION(DTCM_BASE, REGION_16KiB)
- .word MAKE_REGION(BOOT9_BASE, REGION_64KiB)
+ .4byte MAKE_REGION(ITCM_KERNEL_MIRROR, REGION_32KiB)
+ .4byte MAKE_REGION(A9_RAM_BASE, REGION_2MiB)
+ .4byte MAKE_REGION(IO_MEM_ARM9_ONLY, REGION_2MiB)
+ .4byte MAKE_REGION(VRAM_BASE, REGION_8MiB)
+ .4byte MAKE_REGION(DSP_MEM_BASE, REGION_1MiB)
+ .4byte MAKE_REGION(FCRAM_BASE, REGION_256MiB)
+ .4byte MAKE_REGION(DTCM_BASE, REGION_16KiB)
+ .4byte MAKE_REGION(BOOT9_BASE, REGION_64KiB)
_mpu_permissions:
@ Data access permissions:
@ Region 0: User = --, Privileged = RW
@@ -287,7 +278,7 @@ _mpu_permissions:
@ Region 5: User = --, Privileged = RW
@ Region 6: User = --, Privileged = RW
@ Region 7: User = --, Privileged = RO
- .word MAKE_PERMISSIONS(PER_PRIV_RW_USR_NA, PER_PRIV_RW_USR_NA,
+ .4byte MAKE_PERMISSIONS(PER_PRIV_RW_USR_NA, PER_PRIV_RW_USR_NA,
PER_PRIV_RW_USR_NA, PER_PRIV_RW_USR_NA,
PER_PRIV_RW_USR_NA, PER_PRIV_RW_USR_NA,
PER_PRIV_RW_USR_NA, PER_PRIV_RO_USR_NA)
@@ -300,23 +291,20 @@ _mpu_permissions:
@ Region 5: User = --, Privileged = --
@ Region 6: User = --, Privileged = --
@ Region 7: User = --, Privileged = RO
- .word MAKE_PERMISSIONS(PER_PRIV_RO_USR_NA, PER_PRIV_RO_USR_NA,
+ .4byte MAKE_PERMISSIONS(PER_PRIV_RO_USR_NA, PER_PRIV_RO_USR_NA,
PER_NA, PER_NA,
PER_NA, PER_NA,
PER_NA, PER_PRIV_RO_USR_NA)
-.pool
+END_ASM_FUNC
@ Needed by libc
-.align 2
-_init:
+BEGIN_ASM_FUNC _init, thumb
bx lr
-
-.pool
+END_ASM_FUNC
-.align 2
-deinitCpu:
+BEGIN_ASM_FUNC deinitCpu
mov r3, lr
msr cpsr_cxsf, #PSR_INT_OFF | PSR_SYS_MODE
@@ -341,3 +329,4 @@ deinitCpu:
bx r3
.pool
+END_ASM_FUNC
diff --git a/source/mmio.s b/source/mmio.s
index c395ee1..40bbd55 100644
--- a/source/mmio.s
+++ b/source/mmio.s
@@ -16,18 +16,17 @@
* along with this program. If not, see .
*/
- @ Based on https://github.com/AuroraWright/Luma3DS/blob/master/arm9/source/alignedseqmemcpy.s
+@ Based on https://github.com/AuroraWright/Luma3DS/blob/master/arm9/source/alignedseqmemcpy.s
-#include "asmfunc.h"
+#include "asm_macros.h"
-.arm
.cpu arm946e-s
.fpu softvfp
@ void iomemcpy(vu32 *restrict dst, const vu32 *restrict src, u32 size)
-ASM_FUNC iomemcpy
+BEGIN_ASM_FUNC iomemcpy
bics r12, r2, #31
beq iomemcpy_test_words
stmfd sp!, {r4-r10}
@@ -53,10 +52,11 @@ iomemcpy_halfword_byte:
ldrneb r3, [r1]
strneb r3, [r0]
bx lr
+END_ASM_FUNC
@ void iomemset(vu32 *ptr, u32 value, u32 size)
-ASM_FUNC iomemset
+BEGIN_ASM_FUNC iomemset
bics r12, r2, #31
beq iomemset_test_words
stmfd sp!, {r4-r9}
@@ -85,3 +85,4 @@ iomemset_halfword_byte:
tst r2, #1
strneb r1, [r0]
bx lr
+END_ASM_FUNC