diff --git a/include/arm11/drivers/performance_monitor.h b/include/arm11/drivers/performance_monitor.h index 25a4f19..04ef8bc 100644 --- a/include/arm11/drivers/performance_monitor.h +++ b/include/arm11/drivers/performance_monitor.h @@ -20,7 +20,9 @@ // Based on ARM11 MPCore™ Processor Revision: r2p0 Technical Reference Manual (DDI0360F_arm11_mpcore_r2p0_trm.pdf). +#if !__ASSEMBLER__ #include "types.h" +#endif // #if !__ASSEMBLER__ // Performance Monitor Control Register (PMNC). @@ -35,36 +37,35 @@ #define PM_PMN0_IRQ (1u<<8) // Count Register 0 overflow flag. Write 1 to clear. #define PM_PMN1_IRQ (1u<<9) // Count Register 1 overflow flag. Write 1 to clear. #define PM_CCNT_IRQ (1u<<10) // Cycle Counter Register overflow flag. Write 1 to clear. -#define PM_EVT(pmn1, pmn0) ((pmn0)<<20 | (pmn1)<<12) // Set what events PMN0/1 count. See enum below. +#define PM_EVT(pmn1, pmn0) ((pmn0)<<20 | (pmn1)<<12) // Set what events PMN0/1 count. See events below. -enum -{ - PM_EVT_ICACHE_MISS = 0x00u, // Instruction cache miss to a cachable location requires fetch from external memory. - PM_EVT_INST_BUF_STALL = 0x01u, // Stall because instruction buffer cannot deliver an instruction. This can indicate an instruction cache miss or an instruction MicroTLB miss. This event occurs every cycle where the condition is present. - PM_EVT_DATA_DEP_STALL = 0x02u, // Stall because of a data dependency. This event occurs every cycle where the condition is present. - PM_EVT_INST_MICROTLB_MISS = 0x03u, // Instruction MicroTLB miss. - PM_EVT_DATA_MICROTLB_MISS = 0x04u, // Data MicroTLB miss. - PM_EVT_BRANCH_EXEC = 0x05u, // Branch instruction executed, branch might or might not have changed program flow. - PM_EVT_BRANCH_NOT_PRED = 0x06u, // Branch not predicted. - PM_EVT_BRANCH_MISPRED = 0x07u, // Branch mispredicted. - PM_EVT_INST_EXEC = 0x08u, // Instruction executed. - PM_EVT_FOLD_INST_EXEC = 0x09u, // Folded instruction executed. - PM_EVT_DCACHE_RD = 0x0Au, // Data cache read access, not including cache operations. This event occurs for each non-sequential access to a cache line. - PM_EVT_DCACHE_RD_MISS = 0x0Bu, // Data cache read miss, not including cache operations. - PM_EVT_DCACHE_WR = 0x0Cu, // Data cache write access. - PM_EVT_DCACHE_WR_MISS = 0x0Du, // Data cache write miss. - PM_EVT_DCACHE_LINE_EVICT = 0x0Eu, // Data cache line eviction, not including cache operations. - PM_EVT_PC_CHANGE_NOT_MODE = 0x0Fu, // Software changed the PC and there is not a mode change. - PM_EVT_TLB_MISS = 0x10u, // Main TLB miss. - PM_EVT_EXT_MEM_REQ = 0x11u, // External memory request (cache refill, noncachable, write-back). - PM_EVT_LD_ST_UNIT_STALL = 0x12u, // Stall because of Load Store Unit request queue being full. - PM_EVT_ST_BUF_DRAIN = 0x13u, // The number of times the Store buffer was drained because of LSU ordering constraints or CP15 operations. - PM_EVT_BUF_WR_MERGED = 0x14u, // Buffered write merged in a store buffer slot. - PM_EVT_CYCLE = 0xFFu // An increment each cycle. -}; +// Performance monitor events. +#define PM_EVT_ICACHE_MISS (0x00u) // Instruction cache miss to a cachable location requires fetch from external memory. +#define PM_EVT_INST_BUF_STALL (0x01u) // Stall because instruction buffer cannot deliver an instruction. This can indicate an instruction cache miss or an instruction MicroTLB miss. This event occurs every cycle where the condition is present. +#define PM_EVT_DATA_DEP_STALL (0x02u) // Stall because of a data dependency. This event occurs every cycle where the condition is present. +#define PM_EVT_INST_MICROTLB_MISS (0x03u) // Instruction MicroTLB miss. +#define PM_EVT_DATA_MICROTLB_MISS (0x04u) // Data MicroTLB miss. +#define PM_EVT_BRANCH_EXEC (0x05u) // Branch instruction executed, branch might or might not have changed program flow. +#define PM_EVT_BRANCH_NOT_PRED (0x06u) // Branch not predicted. +#define PM_EVT_BRANCH_MISPRED (0x07u) // Branch mispredicted. +#define PM_EVT_INST_EXEC (0x08u) // Instruction executed. +#define PM_EVT_FOLD_INST_EXEC (0x09u) // Folded instruction executed. +#define PM_EVT_DCACHE_RD (0x0Au) // Data cache read access, not including cache operations. This event occurs for each non-sequential access to a cache line. +#define PM_EVT_DCACHE_RD_MISS (0x0Bu) // Data cache read miss, not including cache operations. +#define PM_EVT_DCACHE_WR (0x0Cu) // Data cache write access. +#define PM_EVT_DCACHE_WR_MISS (0x0Du) // Data cache write miss. +#define PM_EVT_DCACHE_LINE_EVICT (0x0Eu) // Data cache line eviction, not including cache operations. +#define PM_EVT_PC_CHANGE_NOT_MODE (0x0Fu) // Software changed the PC and there is not a mode change. +#define PM_EVT_TLB_MISS (0x10u) // Main TLB miss. +#define PM_EVT_EXT_MEM_REQ (0x11u) // External memory request (cache refill, noncachable, write-back). +#define PM_EVT_LD_ST_UNIT_STALL (0x12u) // Stall because of Load Store Unit request queue being full. +#define PM_EVT_ST_BUF_DRAIN (0x13u) // The number of times the Store buffer was drained because of LSU ordering constraints or CP15 operations. +#define PM_EVT_BUF_WR_MERGED (0x14u) // Buffered write merged in a store buffer slot. +#define PM_EVT_CYCLE (0xFFu) // An increment each cycle. +#if !__ASSEMBLER__ // Write Performance Monitor Control Register. ALWAYS_INLINE void __setPmnc(u32 val) { @@ -131,3 +132,4 @@ ALWAYS_INLINE void perfMonitorCountCycles(void) __setPmnc(PM_EVT(PM_EVT_INST_EXEC, PM_EVT_ICACHE_MISS) | PM_CCNT_IRQ | PM_PMN1_IRQ | PM_PMN0_IRQ | PM_CCNT_NODIV | PM_CCNT_RST | PM_PMN01_RST | PM_EN); } +#endif // #if !__ASSEMBLER__ diff --git a/source/arm11/start.s b/source/arm11/start.s index b99c43e..49510a0 100644 --- a/source/arm11/start.s +++ b/source/arm11/start.s @@ -18,6 +18,7 @@ #include "arm.h" #include "mem_map.h" +#include "arm11/drivers/performance_monitor.h" .cpu mpcore .fpu vfpv2 @@ -127,7 +128,8 @@ BEGIN_ASM_FUNC _start blx __libc_init_array @ Initialize ctors and dtors blx PDN_core123Init _start_skip_bss_init_array: - ldrh r2, =0x706 @ Disable + reset all counters. Cycle counter divider 1. IRQs disabled. + @ Disable + reset all performance monitor counters. Acknowledge IRQs. + ldrh r2, =PM_CCNT_IRQ | PM_PMN1_IRQ | PM_PMN0_IRQ | PM_CCNT_RST | PM_PMN01_RST mcr p15, 0, r2, c15, c12, 0 @ Write Performance Monitor Control Register blx setupMmu bl setupVfp