mirror of https://github.com/mgba-emu/mgba.git
105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
#ifndef ISA_INLINES_H
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#define ISA_INLINES_H
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#include "arm.h"
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#define UNUSED(V) (void)(V)
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#define DO_4(DIRECTIVE) \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE
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#define DO_8(DIRECTIVE) \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE, \
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DIRECTIVE
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#define DO_256(DIRECTIVE) \
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DO_4(DO_8(DO_8(DIRECTIVE)))
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#define DO_INTERLACE(LEFT, RIGHT) \
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LEFT, \
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RIGHT
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#define ARM_COND_EQ (cpu->cpsr.z)
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#define ARM_COND_NE (!cpu->cpsr.z)
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#define ARM_COND_CS (cpu->cpsr.c)
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#define ARM_COND_CC (!cpu->cpsr.c)
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#define ARM_COND_MI (cpu->cpsr.n)
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#define ARM_COND_PL (!cpu->cpsr.n)
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#define ARM_COND_VS (cpu->cpsr.v)
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#define ARM_COND_VC (!cpu->cpsr.v)
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#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
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#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
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#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
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#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
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#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
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#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
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#define ARM_COND_AL 1
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#define ARM_SIGN(I) ((I) >> 31)
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#define ARM_ROR(I, ROTATE) ((((uint32_t) (I)) >> ROTATE) | ((I) << (32 - ROTATE)))
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#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
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#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
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#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
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#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
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#define ARM_WAIT_MUL(R) \
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if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
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cpu->cycles += 1; \
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} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
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cpu->cycles += 2; \
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} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
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cpu->cycles += 3; \
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} else { \
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cpu->cycles += 4; \
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}
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#define ARM_STUB cpu->board->hitStub(cpu->board, opcode)
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#define ARM_ILL cpu->board->hitIllegal(cpu->board, opcode)
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#define ARM_WRITE_PC \
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cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM) + WORD_SIZE_ARM; \
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cpu->memory->setActiveRegion(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM); \
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currentCycles += 2 + cpu->memory->activeNonseqCycles32 + cpu->memory->activePrefetchCycles32;
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#define THUMB_WRITE_PC \
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cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB) + WORD_SIZE_THUMB; \
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cpu->memory->setActiveRegion(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_THUMB); \
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currentCycles += 2 + cpu->memory->activeNonseqCycles16 + cpu->memory->activePrefetchCycles16;
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static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
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return mode != MODE_SYSTEM && mode != MODE_USER;
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}
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static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
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if (executionMode == cpu->executionMode) {
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return;
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}
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cpu->executionMode = executionMode;
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switch (executionMode) {
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case MODE_ARM:
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cpu->cpsr.t = 0;
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break;
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case MODE_THUMB:
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cpu->cpsr.t = 1;
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}
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}
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static inline void _ARMReadCPSR(struct ARMCore* cpu) {
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_ARMSetMode(cpu, cpu->cpsr.t);
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ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
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cpu->board->readCPSR(cpu->board);
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}
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#endif
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