mirror of https://github.com/mgba-emu/mgba.git
224 lines
5.3 KiB
Plaintext
224 lines
5.3 KiB
Plaintext
; this file was created with wlalink by ville helin <vhelin@iki.fi>.
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; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing.gb".
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[labels]
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01:4bff print_load_font
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01:4c0c print_string
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01:4c16 print_a
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01:4c20 print_newline
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01:4c2b print_digit
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01:4c38 print_regs
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01:4c41 _print_sl_data0
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01:4c47 _print_sl_out0
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01:4c54 _print_sl_data1
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01:4c5a _print_sl_out1
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01:4c6c _print_sl_data2
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01:4c72 _print_sl_out2
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01:4c7f _print_sl_data3
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01:4c85 _print_sl_out3
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01:4c97 _print_sl_data4
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01:4c9d _print_sl_out4
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01:4caa _print_sl_data5
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01:4cb0 _print_sl_out5
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01:4cc2 _print_sl_data6
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01:4cc8 _print_sl_out6
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01:4cd5 _print_sl_data7
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01:4cdb _print_sl_out7
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01:4000 font
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00:c000 regs_save
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00:c000 regs_save.f
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00:c001 regs_save.a
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00:c002 regs_save.c
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00:c003 regs_save.b
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00:c004 regs_save.e
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00:c005 regs_save.d
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00:c006 regs_save.l
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00:c007 regs_save.h
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00:c008 regs_flags
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00:c009 regs_assert
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00:c009 regs_assert.f
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00:c00a regs_assert.a
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00:c00b regs_assert.c
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00:c00c regs_assert.b
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00:c00d regs_assert.e
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00:c00e regs_assert.d
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00:c00f regs_assert.l
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00:c010 regs_assert.h
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00:c011 memdump_len
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00:c012 memdump_addr
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01:47f0 memcpy
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01:47f9 memset
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01:4802 memcmp
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01:4810 clear_vram
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01:481a clear_oam
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01:4824 disable_lcd_safe
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01:482a _wait_ly_0
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01:4830 _wait_ly_1
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01:4839 reset_screen
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01:484d process_results
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01:4861 _wait_ly_2
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01:4867 _wait_ly_3
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01:487d _print_results_halt_0
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01:4880 _process_results_cb
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01:488b _print_sl_data8
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01:4895 _print_sl_out8
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01:48af _print_sl_data9
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01:48ba _print_sl_out9
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01:48d2 _print_sl_data10
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01:48de _print_sl_out10
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01:48df dump_mem
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01:48fe _dump_mem_line
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01:4928 _check_asserts
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01:4936 _print_sl_data11
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01:4939 _print_sl_out11
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01:4945 _print_sl_data12
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01:4947 _print_sl_out12
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01:494f _print_sl_data13
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01:4952 _print_sl_out13
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01:495c __check_assert_fail0
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01:4967 _print_sl_data14
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01:496a _print_sl_out14
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01:496d __check_assert_ok0
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01:4975 _print_sl_data15
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01:497a _print_sl_out15
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01:497c __check_assert_skip0
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01:4984 _print_sl_data16
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01:498c _print_sl_out16
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01:498c __check_assert_out0
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01:4998 _print_sl_data17
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01:499a _print_sl_out17
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01:49a2 _print_sl_data18
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01:49a5 _print_sl_out18
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01:49af __check_assert_fail1
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01:49ba _print_sl_data19
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01:49bd _print_sl_out19
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01:49c0 __check_assert_ok1
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01:49c8 _print_sl_data20
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01:49cd _print_sl_out20
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01:49cf __check_assert_skip1
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01:49d7 _print_sl_data21
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01:49df _print_sl_out21
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01:49df __check_assert_out1
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01:49ea _print_sl_data22
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01:49ed _print_sl_out22
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01:49f9 _print_sl_data23
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01:49fb _print_sl_out23
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01:4a03 _print_sl_data24
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01:4a06 _print_sl_out24
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01:4a10 __check_assert_fail2
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01:4a1b _print_sl_data25
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01:4a1e _print_sl_out25
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01:4a21 __check_assert_ok2
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01:4a29 _print_sl_data26
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01:4a2e _print_sl_out26
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01:4a30 __check_assert_skip2
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01:4a38 _print_sl_data27
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01:4a40 _print_sl_out27
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01:4a40 __check_assert_out2
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01:4a4c _print_sl_data28
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01:4a4e _print_sl_out28
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01:4a56 _print_sl_data29
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01:4a59 _print_sl_out29
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01:4a63 __check_assert_fail3
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01:4a6e _print_sl_data30
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01:4a71 _print_sl_out30
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01:4a74 __check_assert_ok3
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01:4a7c _print_sl_data31
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01:4a81 _print_sl_out31
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01:4a83 __check_assert_skip3
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01:4a8b _print_sl_data32
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01:4a93 _print_sl_out32
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01:4a93 __check_assert_out3
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01:4a9e _print_sl_data33
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01:4aa1 _print_sl_out33
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01:4aad _print_sl_data34
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01:4aaf _print_sl_out34
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01:4ab7 _print_sl_data35
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01:4aba _print_sl_out35
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01:4ac4 __check_assert_fail4
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01:4acf _print_sl_data36
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01:4ad2 _print_sl_out36
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01:4ad5 __check_assert_ok4
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01:4add _print_sl_data37
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01:4ae2 _print_sl_out37
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01:4ae4 __check_assert_skip4
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01:4aec _print_sl_data38
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01:4af4 _print_sl_out38
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01:4af4 __check_assert_out4
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01:4b00 _print_sl_data39
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01:4b02 _print_sl_out39
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01:4b0a _print_sl_data40
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01:4b0d _print_sl_out40
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01:4b17 __check_assert_fail5
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01:4b22 _print_sl_data41
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01:4b25 _print_sl_out41
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01:4b28 __check_assert_ok5
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01:4b30 _print_sl_data42
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01:4b35 _print_sl_out42
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01:4b37 __check_assert_skip5
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01:4b3f _print_sl_data43
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01:4b47 _print_sl_out43
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01:4b47 __check_assert_out5
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01:4b52 _print_sl_data44
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01:4b55 _print_sl_out44
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01:4b61 _print_sl_data45
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01:4b63 _print_sl_out45
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01:4b6b _print_sl_data46
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01:4b6e _print_sl_out46
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01:4b78 __check_assert_fail6
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01:4b83 _print_sl_data47
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01:4b86 _print_sl_out47
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01:4b89 __check_assert_ok6
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01:4b91 _print_sl_data48
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01:4b96 _print_sl_out48
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01:4b98 __check_assert_skip6
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01:4ba0 _print_sl_data49
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01:4ba8 _print_sl_out49
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01:4ba8 __check_assert_out6
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01:4bb4 _print_sl_data50
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01:4bb6 _print_sl_out50
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01:4bbe _print_sl_data51
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01:4bc1 _print_sl_out51
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01:4bcb __check_assert_fail7
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01:4bd6 _print_sl_data52
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01:4bd9 _print_sl_out52
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01:4bdc __check_assert_ok7
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01:4be4 _print_sl_data53
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01:4be9 _print_sl_out53
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01:4beb __check_assert_skip7
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01:4bf3 _print_sl_data54
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01:4bfb _print_sl_out54
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01:4bfb __check_assert_out7
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00:0151 _wait_ly_4
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00:0157 _wait_ly_5
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00:0184 test_finish
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00:0198 _wait_ly_6
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00:019e _wait_ly_7
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00:01b4 _print_results_halt_1
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00:01b7 _test_ok_cb_0
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00:01bf _print_sl_data55
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00:01c7 _print_sl_out55
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00:01ca wram_test
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00:01cd fail_round1
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00:01e1 _wait_ly_8
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00:01e7 _wait_ly_9
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00:01fd _print_results_halt_2
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00:0200 _test_failure_cb_0
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00:0208 _print_sl_data56
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00:0216 _print_sl_out56
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00:0219 fail_round2
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00:022d _wait_ly_10
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00:0233 _wait_ly_11
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00:0249 _print_results_halt_3
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00:024c _test_failure_cb_1
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00:0254 _print_sl_data57
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00:0262 _print_sl_out57
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00:1f80 hiram_test
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00:1f87 _wait_ly_12
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00:1f8d _wait_ly_13
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00:1fa1 test_round2
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00:1fa8 _wait_ly_14
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00:1fae _wait_ly_15
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00:1fca finish_round1
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00:1ada finish_round2
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