mirror of https://github.com/mgba-emu/mgba.git
729 lines
17 KiB
C
729 lines
17 KiB
C
/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include <mgba/internal/gb/io.h>
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#include <mgba/internal/gb/gb.h>
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#include <mgba/internal/gb/sio.h>
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#include <mgba/internal/gb/serialize.h>
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mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
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const char* const GBIORegisterNames[] = {
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[REG_JOYP] = "JOYP",
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[REG_SB] = "SB",
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[REG_SC] = "SC",
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[REG_DIV] = "DIV",
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[REG_TIMA] = "TIMA",
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[REG_TMA] = "TMA",
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[REG_TAC] = "TAC",
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[REG_IF] = "IF",
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[REG_NR10] = "NR10",
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[REG_NR11] = "NR11",
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[REG_NR12] = "NR12",
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[REG_NR13] = "NR13",
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[REG_NR14] = "NR14",
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[REG_NR21] = "NR21",
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[REG_NR22] = "NR22",
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[REG_NR23] = "NR23",
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[REG_NR24] = "NR24",
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[REG_NR30] = "NR30",
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[REG_NR31] = "NR31",
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[REG_NR32] = "NR32",
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[REG_NR33] = "NR33",
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[REG_NR34] = "NR34",
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[REG_NR41] = "NR41",
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[REG_NR42] = "NR42",
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[REG_NR43] = "NR43",
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[REG_NR44] = "NR44",
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[REG_NR50] = "NR50",
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[REG_NR51] = "NR51",
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[REG_NR52] = "NR52",
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[REG_LCDC] = "LCDC",
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[REG_STAT] = "STAT",
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[REG_SCY] = "SCY",
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[REG_SCX] = "SCX",
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[REG_LY] = "LY",
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[REG_LYC] = "LYC",
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[REG_DMA] = "DMA",
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[REG_BGP] = "BGP",
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[REG_OBP0] = "OBP0",
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[REG_OBP1] = "OBP1",
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[REG_WY] = "WY",
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[REG_WX] = "WX",
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[REG_KEY1] = "KEY1",
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[REG_VBK] = "VBK",
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[REG_HDMA1] = "HDMA1",
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[REG_HDMA2] = "HDMA2",
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[REG_HDMA3] = "HDMA3",
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[REG_HDMA4] = "HDMA4",
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[REG_HDMA5] = "HDMA5",
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[REG_RP] = "RP",
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[REG_BCPS] = "BCPS",
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[REG_BCPD] = "BCPD",
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[REG_OCPS] = "OCPS",
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[REG_OCPD] = "OCPD",
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[REG_SVBK] = "SVBK",
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[REG_IE] = "IE",
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};
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static const uint8_t _registerMask[] = {
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[REG_SC] = 0x7E, // TODO: GBC differences
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[REG_IF] = 0xE0,
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[REG_TAC] = 0xF8,
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[REG_NR10] = 0x80,
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[REG_NR11] = 0x3F,
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[REG_NR12] = 0x00,
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[REG_NR13] = 0xFF,
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[REG_NR14] = 0xBF,
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[REG_NR21] = 0x3F,
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[REG_NR22] = 0x00,
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[REG_NR23] = 0xFF,
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[REG_NR24] = 0xBF,
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[REG_NR30] = 0x7F,
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[REG_NR31] = 0xFF,
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[REG_NR32] = 0x9F,
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[REG_NR33] = 0xFF,
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[REG_NR34] = 0xBF,
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[REG_NR41] = 0xFF,
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[REG_NR42] = 0x00,
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[REG_NR43] = 0x00,
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[REG_NR44] = 0xBF,
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[REG_NR50] = 0x00,
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[REG_NR51] = 0x00,
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[REG_NR52] = 0x70,
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[REG_STAT] = 0x80,
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[REG_KEY1] = 0x7E,
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[REG_VBK] = 0xFE,
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[REG_OCPS] = 0x40,
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[REG_BCPS] = 0x40,
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[REG_UNK6C] = 0xFE,
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[REG_SVBK] = 0xF8,
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[REG_IE] = 0xE0,
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};
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static uint8_t _readKeys(struct GB* gb);
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static uint8_t _readKeysFiltered(struct GB* gb);
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static void _writeSGBBits(struct GB* gb, int bits) {
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if (!bits) {
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gb->sgbBit = -1;
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memset(gb->sgbPacket, 0, sizeof(gb->sgbPacket));
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}
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if (bits == gb->currentSgbBits) {
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return;
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}
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gb->currentSgbBits = bits;
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if (gb->sgbBit > 128) {
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switch (bits) {
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case 1:
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gb->sgbBit |= 2;
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break;
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case 2:
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gb->sgbBit |= 4;
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break;
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case 3:
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if (gb->sgbBit == 135) {
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gb->sgbBit &= ~6;
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gb->sgbCurrentController = (gb->sgbCurrentController + 1) & gb->sgbControllers;
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}
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break;
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}
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}
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if (gb->sgbBit == 128 && bits == 2) {
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GBVideoWriteSGBPacket(&gb->video, gb->sgbPacket);
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++gb->sgbBit;
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}
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if (gb->sgbBit >= 128) {
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return;
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}
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switch (bits) {
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case 1:
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if (gb->sgbBit < 0) {
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return;
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}
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gb->sgbPacket[gb->sgbBit >> 3] |= 1 << (gb->sgbBit & 7);
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break;
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case 3:
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++gb->sgbBit;
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default:
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break;
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}
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}
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void GBIOInit(struct GB* gb) {
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memset(gb->memory.io, 0, sizeof(gb->memory.io));
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}
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void GBIOReset(struct GB* gb) {
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memset(gb->memory.io, 0, sizeof(gb->memory.io));
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GBIOWrite(gb, REG_TIMA, 0);
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GBIOWrite(gb, REG_TMA, 0);
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GBIOWrite(gb, REG_TAC, 0);
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GBIOWrite(gb, REG_IF, 1);
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GBIOWrite(gb, REG_NR52, 0xF1);
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GBIOWrite(gb, REG_NR14, 0x3F);
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GBIOWrite(gb, REG_NR10, 0x80);
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GBIOWrite(gb, REG_NR11, 0xBF);
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GBIOWrite(gb, REG_NR12, 0xF3);
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GBIOWrite(gb, REG_NR13, 0xF3);
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GBIOWrite(gb, REG_NR24, 0x3F);
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GBIOWrite(gb, REG_NR21, 0x3F);
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GBIOWrite(gb, REG_NR22, 0x00);
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GBIOWrite(gb, REG_NR34, 0x3F);
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GBIOWrite(gb, REG_NR30, 0x7F);
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GBIOWrite(gb, REG_NR31, 0xFF);
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GBIOWrite(gb, REG_NR32, 0x9F);
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GBIOWrite(gb, REG_NR44, 0x3F);
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GBIOWrite(gb, REG_NR41, 0xFF);
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GBIOWrite(gb, REG_NR42, 0x00);
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GBIOWrite(gb, REG_NR43, 0x00);
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GBIOWrite(gb, REG_NR50, 0x77);
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GBIOWrite(gb, REG_NR51, 0xF3);
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if (!gb->biosVf) {
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GBIOWrite(gb, REG_LCDC, 0x91);
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} else {
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GBIOWrite(gb, REG_LCDC, 0x00);
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}
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GBIOWrite(gb, REG_SCY, 0x00);
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GBIOWrite(gb, REG_SCX, 0x00);
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GBIOWrite(gb, REG_LYC, 0x00);
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GBIOWrite(gb, REG_DMA, 0xFF);
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GBIOWrite(gb, REG_BGP, 0xFC);
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if (gb->model < GB_MODEL_CGB) {
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GBIOWrite(gb, REG_OBP0, 0xFF);
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GBIOWrite(gb, REG_OBP1, 0xFF);
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}
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GBIOWrite(gb, REG_WY, 0x00);
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GBIOWrite(gb, REG_WX, 0x00);
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if (gb->model & GB_MODEL_CGB) {
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GBIOWrite(gb, REG_UNK4C, 0);
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GBIOWrite(gb, REG_JOYP, 0xFF);
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GBIOWrite(gb, REG_VBK, 0);
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GBIOWrite(gb, REG_BCPS, 0);
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GBIOWrite(gb, REG_OCPS, 0);
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GBIOWrite(gb, REG_SVBK, 1);
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GBIOWrite(gb, REG_HDMA1, 0xFF);
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GBIOWrite(gb, REG_HDMA2, 0xFF);
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GBIOWrite(gb, REG_HDMA3, 0xFF);
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GBIOWrite(gb, REG_HDMA4, 0xFF);
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gb->memory.io[REG_HDMA5] = 0xFF;
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} else if (gb->model & GB_MODEL_SGB) {
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GBIOWrite(gb, REG_JOYP, 0xFF);
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}
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GBIOWrite(gb, REG_IE, 0x00);
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}
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void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
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switch (address) {
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case REG_SB:
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GBSIOWriteSB(&gb->sio, value);
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break;
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case REG_SC:
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GBSIOWriteSC(&gb->sio, value);
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break;
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case REG_DIV:
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GBTimerDivReset(&gb->timer);
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return;
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case REG_NR10:
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if (gb->audio.enable) {
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GBAudioWriteNR10(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR11:
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if (gb->audio.enable) {
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GBAudioWriteNR11(&gb->audio, value);
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} else {
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if (gb->audio.style == GB_AUDIO_DMG) {
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GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
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}
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value = 0;
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}
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break;
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case REG_NR12:
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if (gb->audio.enable) {
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GBAudioWriteNR12(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR13:
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if (gb->audio.enable) {
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GBAudioWriteNR13(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR14:
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if (gb->audio.enable) {
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GBAudioWriteNR14(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR21:
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if (gb->audio.enable) {
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GBAudioWriteNR21(&gb->audio, value);
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} else {
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if (gb->audio.style == GB_AUDIO_DMG) {
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GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
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}
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value = 0;
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}
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break;
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case REG_NR22:
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if (gb->audio.enable) {
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GBAudioWriteNR22(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR23:
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if (gb->audio.enable) {
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GBAudioWriteNR23(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR24:
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if (gb->audio.enable) {
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GBAudioWriteNR24(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR30:
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if (gb->audio.enable) {
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GBAudioWriteNR30(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR31:
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if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
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GBAudioWriteNR31(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR32:
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if (gb->audio.enable) {
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GBAudioWriteNR32(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR33:
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if (gb->audio.enable) {
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GBAudioWriteNR33(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR34:
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if (gb->audio.enable) {
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GBAudioWriteNR34(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR41:
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if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
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GBAudioWriteNR41(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR42:
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if (gb->audio.enable) {
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GBAudioWriteNR42(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR43:
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if (gb->audio.enable) {
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GBAudioWriteNR43(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR44:
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if (gb->audio.enable) {
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GBAudioWriteNR44(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR50:
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if (gb->audio.enable) {
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GBAudioWriteNR50(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR51:
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if (gb->audio.enable) {
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GBAudioWriteNR51(&gb->audio, value);
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} else {
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value = 0;
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}
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break;
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case REG_NR52:
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GBAudioWriteNR52(&gb->audio, value);
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value &= 0x80;
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value |= gb->memory.io[REG_NR52] & 0x0F;
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break;
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case REG_WAVE_0:
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case REG_WAVE_1:
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case REG_WAVE_2:
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case REG_WAVE_3:
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case REG_WAVE_4:
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case REG_WAVE_5:
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case REG_WAVE_6:
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case REG_WAVE_7:
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case REG_WAVE_8:
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case REG_WAVE_9:
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case REG_WAVE_A:
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case REG_WAVE_B:
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case REG_WAVE_C:
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case REG_WAVE_D:
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case REG_WAVE_E:
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case REG_WAVE_F:
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if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
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gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
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} else if(gb->audio.ch3.readable) {
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gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
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}
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break;
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case REG_JOYP:
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gb->memory.io[REG_JOYP] = value | 0x0F;
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_readKeys(gb);
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if (gb->model & GB_MODEL_SGB) {
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_writeSGBBits(gb, (value >> 4) & 3);
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}
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return;
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case REG_TIMA:
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if (value && mTimingUntil(&gb->timing, &gb->timer.irq) > 1) {
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mTimingDeschedule(&gb->timing, &gb->timer.irq);
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}
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if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
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return;
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}
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break;
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case REG_TMA:
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if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
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gb->memory.io[REG_TIMA] = value;
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}
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break;
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case REG_TAC:
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value = GBTimerUpdateTAC(&gb->timer, value);
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break;
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case REG_IF:
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gb->memory.io[REG_IF] = value | 0xE0;
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GBUpdateIRQs(gb);
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return;
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case REG_LCDC:
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// TODO: handle GBC differences
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GBVideoProcessDots(&gb->video, 0);
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value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
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GBVideoWriteLCDC(&gb->video, value);
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break;
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case REG_LYC:
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GBVideoWriteLYC(&gb->video, value);
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break;
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case REG_DMA:
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GBMemoryDMA(gb, value << 8);
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break;
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case REG_SCY:
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case REG_SCX:
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case REG_WY:
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case REG_WX:
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GBVideoProcessDots(&gb->video, 0);
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value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
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break;
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case REG_BGP:
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case REG_OBP0:
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case REG_OBP1:
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GBVideoProcessDots(&gb->video, 0);
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GBVideoWritePalette(&gb->video, address, value);
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break;
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case REG_STAT:
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GBVideoWriteSTAT(&gb->video, value);
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value = gb->video.stat;
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break;
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case 0x50:
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GBUnmapBIOS(gb);
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if (gb->model >= GB_MODEL_CGB && gb->memory.io[REG_UNK4C] < 0x80) {
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gb->model = GB_MODEL_DMG;
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GBVideoDisableCGB(&gb->video);
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}
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break;
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case REG_IE:
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gb->memory.ie = value;
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GBUpdateIRQs(gb);
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return;
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default:
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if (gb->model >= GB_MODEL_CGB) {
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switch (address) {
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case REG_UNK4C:
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break;
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case REG_KEY1:
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value &= 0x1;
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value |= gb->memory.io[address] & 0x80;
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break;
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case REG_VBK:
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GBVideoSwitchBank(&gb->video, value);
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break;
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case REG_HDMA1:
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case REG_HDMA2:
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case REG_HDMA3:
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case REG_HDMA4:
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// Handled transparently by the registers
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break;
|
|
case REG_HDMA5:
|
|
value = GBMemoryWriteHDMA5(gb, value);
|
|
break;
|
|
case REG_BCPS:
|
|
gb->video.bcpIndex = value & 0x3F;
|
|
gb->video.bcpIncrement = value & 0x80;
|
|
gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
|
|
break;
|
|
case REG_BCPD:
|
|
if (gb->video.mode != 3) {
|
|
GBVideoProcessDots(&gb->video, 0);
|
|
GBVideoWritePalette(&gb->video, address, value);
|
|
}
|
|
return;
|
|
case REG_OCPS:
|
|
gb->video.ocpIndex = value & 0x3F;
|
|
gb->video.ocpIncrement = value & 0x80;
|
|
gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
|
|
break;
|
|
case REG_OCPD:
|
|
if (gb->video.mode != 3) {
|
|
GBVideoProcessDots(&gb->video, 0);
|
|
GBVideoWritePalette(&gb->video, address, value);
|
|
}
|
|
return;
|
|
case REG_SVBK:
|
|
GBMemorySwitchWramBank(&gb->memory, value);
|
|
value = gb->memory.wramCurrentBank;
|
|
break;
|
|
default:
|
|
goto failed;
|
|
}
|
|
goto success;
|
|
}
|
|
failed:
|
|
mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
|
|
if (address >= GB_SIZE_IO) {
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
success:
|
|
gb->memory.io[address] = value;
|
|
}
|
|
|
|
static uint8_t _readKeys(struct GB* gb) {
|
|
uint8_t keys = *gb->keySource;
|
|
if (gb->sgbCurrentController != 0) {
|
|
keys = 0;
|
|
}
|
|
uint8_t joyp = gb->memory.io[REG_JOYP];
|
|
switch (joyp & 0x30) {
|
|
case 0x30:
|
|
keys = gb->sgbCurrentController;
|
|
break;
|
|
case 0x20:
|
|
keys >>= 4;
|
|
break;
|
|
case 0x10:
|
|
break;
|
|
case 0x00:
|
|
keys |= keys >> 4;
|
|
break;
|
|
}
|
|
gb->memory.io[REG_JOYP] = (0xCF | joyp) ^ (keys & 0xF);
|
|
if (joyp & ~gb->memory.io[REG_JOYP] & 0xF) {
|
|
gb->memory.io[REG_IF] |= (1 << GB_IRQ_KEYPAD);
|
|
GBUpdateIRQs(gb);
|
|
}
|
|
return gb->memory.io[REG_JOYP];
|
|
}
|
|
|
|
static uint8_t _readKeysFiltered(struct GB* gb) {
|
|
uint8_t keys = _readKeys(gb);
|
|
if (!gb->allowOpposingDirections && (keys & 0x30) == 0x20) {
|
|
unsigned rl = keys & 0x03;
|
|
unsigned ud = keys & 0x0C;
|
|
if (!rl) {
|
|
keys |= 0x03;
|
|
}
|
|
if (!ud) {
|
|
keys |= 0x0C;
|
|
}
|
|
}
|
|
return keys;
|
|
}
|
|
|
|
uint8_t GBIORead(struct GB* gb, unsigned address) {
|
|
switch (address) {
|
|
case REG_JOYP:
|
|
return _readKeysFiltered(gb);
|
|
case REG_IE:
|
|
return gb->memory.ie;
|
|
case REG_WAVE_0:
|
|
case REG_WAVE_1:
|
|
case REG_WAVE_2:
|
|
case REG_WAVE_3:
|
|
case REG_WAVE_4:
|
|
case REG_WAVE_5:
|
|
case REG_WAVE_6:
|
|
case REG_WAVE_7:
|
|
case REG_WAVE_8:
|
|
case REG_WAVE_9:
|
|
case REG_WAVE_A:
|
|
case REG_WAVE_B:
|
|
case REG_WAVE_C:
|
|
case REG_WAVE_D:
|
|
case REG_WAVE_E:
|
|
case REG_WAVE_F:
|
|
if (gb->audio.playingCh3) {
|
|
if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
|
|
return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
|
|
} else {
|
|
return 0xFF;
|
|
}
|
|
} else {
|
|
return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
|
|
}
|
|
break;
|
|
case REG_SB:
|
|
case REG_SC:
|
|
case REG_IF:
|
|
case REG_NR10:
|
|
case REG_NR11:
|
|
case REG_NR12:
|
|
case REG_NR14:
|
|
case REG_NR21:
|
|
case REG_NR22:
|
|
case REG_NR24:
|
|
case REG_NR30:
|
|
case REG_NR32:
|
|
case REG_NR34:
|
|
case REG_NR41:
|
|
case REG_NR42:
|
|
case REG_NR43:
|
|
case REG_NR44:
|
|
case REG_NR50:
|
|
case REG_NR51:
|
|
case REG_NR52:
|
|
case REG_DIV:
|
|
case REG_TIMA:
|
|
case REG_TMA:
|
|
case REG_TAC:
|
|
case REG_STAT:
|
|
case REG_LCDC:
|
|
case REG_SCY:
|
|
case REG_SCX:
|
|
case REG_LY:
|
|
case REG_LYC:
|
|
case REG_DMA:
|
|
case REG_BGP:
|
|
case REG_OBP0:
|
|
case REG_OBP1:
|
|
case REG_WY:
|
|
case REG_WX:
|
|
// Handled transparently by the registers
|
|
break;
|
|
default:
|
|
if (gb->model >= GB_MODEL_CGB) {
|
|
switch (address) {
|
|
case REG_KEY1:
|
|
case REG_VBK:
|
|
case REG_HDMA1:
|
|
case REG_HDMA2:
|
|
case REG_HDMA3:
|
|
case REG_HDMA4:
|
|
case REG_HDMA5:
|
|
case REG_BCPS:
|
|
case REG_BCPD:
|
|
case REG_OCPS:
|
|
case REG_OCPD:
|
|
case REG_SVBK:
|
|
// Handled transparently by the registers
|
|
goto success;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
|
|
return 0xFF;
|
|
}
|
|
success:
|
|
return gb->memory.io[address] | _registerMask[address];
|
|
}
|
|
|
|
void GBTestKeypadIRQ(struct GB* gb) {
|
|
_readKeys(gb);
|
|
}
|
|
|
|
struct GBSerializedState;
|
|
void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
|
|
memcpy(state->io, gb->memory.io, GB_SIZE_IO);
|
|
state->ie = gb->memory.ie;
|
|
}
|
|
|
|
void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
|
|
memcpy(gb->memory.io, state->io, GB_SIZE_IO);
|
|
gb->memory.ie = state->ie;
|
|
|
|
if (GBAudioEnableGetEnable(*gb->audio.nr52)) {
|
|
GBIOWrite(gb, REG_NR10, gb->memory.io[REG_NR10]);
|
|
GBIOWrite(gb, REG_NR11, gb->memory.io[REG_NR11]);
|
|
GBIOWrite(gb, REG_NR12, gb->memory.io[REG_NR12]);
|
|
GBIOWrite(gb, REG_NR13, gb->memory.io[REG_NR13]);
|
|
gb->audio.ch1.control.frequency &= 0xFF;
|
|
gb->audio.ch1.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR14] << 8);
|
|
gb->audio.ch1.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR14] << 8);
|
|
GBIOWrite(gb, REG_NR21, gb->memory.io[REG_NR21]);
|
|
GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR22]);
|
|
GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR23]);
|
|
gb->audio.ch2.control.frequency &= 0xFF;
|
|
gb->audio.ch2.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR24] << 8);
|
|
gb->audio.ch2.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR24] << 8);
|
|
GBIOWrite(gb, REG_NR30, gb->memory.io[REG_NR30]);
|
|
GBIOWrite(gb, REG_NR31, gb->memory.io[REG_NR31]);
|
|
GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR32]);
|
|
GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR33]);
|
|
gb->audio.ch3.rate &= 0xFF;
|
|
gb->audio.ch3.rate |= GBAudioRegisterControlGetRate(gb->memory.io[REG_NR34] << 8);
|
|
gb->audio.ch3.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR34] << 8);
|
|
GBIOWrite(gb, REG_NR41, gb->memory.io[REG_NR41]);
|
|
GBIOWrite(gb, REG_NR42, gb->memory.io[REG_NR42]);
|
|
GBIOWrite(gb, REG_NR43, gb->memory.io[REG_NR43]);
|
|
gb->audio.ch4.stop = GBAudioRegisterNoiseControlGetStop(gb->memory.io[REG_NR44]);
|
|
GBIOWrite(gb, REG_NR50, gb->memory.io[REG_NR50]);
|
|
GBIOWrite(gb, REG_NR51, gb->memory.io[REG_NR51]);
|
|
}
|
|
|
|
gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
|
|
gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
|
|
gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
|
|
gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
|
|
gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
|
|
if (gb->model & GB_MODEL_SGB) {
|
|
gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_BGP, state->io[REG_BGP]);
|
|
gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP0, state->io[REG_OBP0]);
|
|
gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP1, state->io[REG_OBP1]);
|
|
}
|
|
gb->video.stat = state->io[REG_STAT];
|
|
}
|