mirror of https://github.com/mgba-emu/mgba.git
227 lines
5.4 KiB
Plaintext
227 lines
5.4 KiB
Plaintext
; this file was created with wlalink by ville helin <vhelin@iki.fi>.
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; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/multicart_rom_8Mb.gb".
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[labels]
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01:4001 print_load_font
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01:400e print_string
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01:4018 print_a
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01:4022 print_newline
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01:402d print_digit
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01:403a print_regs
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01:4043 _print_sl_data0
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01:4049 _print_sl_out0
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01:4056 _print_sl_data1
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01:405c _print_sl_out1
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01:406e _print_sl_data2
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01:4074 _print_sl_out2
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01:4081 _print_sl_data3
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01:4087 _print_sl_out3
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01:4099 _print_sl_data4
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01:409f _print_sl_out4
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01:40ac _print_sl_data5
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01:40b2 _print_sl_out5
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01:40c4 _print_sl_data6
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01:40ca _print_sl_out6
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01:40d7 _print_sl_data7
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01:40dd _print_sl_out7
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01:4134 font
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00:c000 regs_save
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00:c000 regs_save.f
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00:c001 regs_save.a
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00:c002 regs_save.c
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00:c003 regs_save.b
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00:c004 regs_save.e
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00:c005 regs_save.d
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00:c006 regs_save.l
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00:c007 regs_save.h
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00:c008 regs_flags
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00:c009 regs_assert
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00:c009 regs_assert.f
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00:c00a regs_assert.a
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00:c00b regs_assert.c
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00:c00c regs_assert.b
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00:c00d regs_assert.e
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00:c00e regs_assert.d
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00:c00f regs_assert.l
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00:c010 regs_assert.h
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00:c011 memdump_len
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00:c012 memdump_addr
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01:4924 memcpy
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01:492d memset
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01:4936 memcmp
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01:4944 clear_vram
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01:494e clear_oam
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01:4958 disable_lcd_safe
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01:495e _wait_ly_0
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01:4964 _wait_ly_1
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01:496d reset_screen
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01:4981 process_results
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01:4995 _wait_ly_2
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01:499b _wait_ly_3
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01:49b1 _print_results_halt_0
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01:49b4 _process_results_cb
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01:49bf _print_sl_data8
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01:49c9 _print_sl_out8
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01:49e3 _print_sl_data9
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01:49ee _print_sl_out9
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01:4a06 _print_sl_data10
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01:4a12 _print_sl_out10
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01:4a13 dump_mem
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01:4a32 _dump_mem_line
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01:4a5c _check_asserts
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01:4a6a _print_sl_data11
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01:4a6d _print_sl_out11
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01:4a79 _print_sl_data12
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01:4a7b _print_sl_out12
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01:4a83 _print_sl_data13
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01:4a86 _print_sl_out13
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01:4a90 __check_assert_fail0
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01:4a9b _print_sl_data14
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01:4a9e _print_sl_out14
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01:4aa1 __check_assert_ok0
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01:4aa9 _print_sl_data15
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01:4aae _print_sl_out15
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01:4ab0 __check_assert_skip0
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01:4ab8 _print_sl_data16
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01:4ac0 _print_sl_out16
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01:4ac0 __check_assert_out0
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01:4acc _print_sl_data17
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01:4ace _print_sl_out17
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01:4ad6 _print_sl_data18
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01:4ad9 _print_sl_out18
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01:4ae3 __check_assert_fail1
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01:4aee _print_sl_data19
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01:4af1 _print_sl_out19
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01:4af4 __check_assert_ok1
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01:4afc _print_sl_data20
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01:4b01 _print_sl_out20
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01:4b03 __check_assert_skip1
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01:4b0b _print_sl_data21
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01:4b13 _print_sl_out21
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01:4b13 __check_assert_out1
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01:4b1e _print_sl_data22
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01:4b21 _print_sl_out22
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01:4b2d _print_sl_data23
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01:4b2f _print_sl_out23
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01:4b37 _print_sl_data24
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01:4b3a _print_sl_out24
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01:4b44 __check_assert_fail2
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01:4b4f _print_sl_data25
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01:4b52 _print_sl_out25
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01:4b55 __check_assert_ok2
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01:4b5d _print_sl_data26
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01:4b62 _print_sl_out26
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01:4b64 __check_assert_skip2
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01:4b6c _print_sl_data27
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01:4b74 _print_sl_out27
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01:4b74 __check_assert_out2
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01:4b80 _print_sl_data28
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01:4b82 _print_sl_out28
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01:4b8a _print_sl_data29
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01:4b8d _print_sl_out29
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01:4b97 __check_assert_fail3
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01:4ba2 _print_sl_data30
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01:4ba5 _print_sl_out30
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01:4ba8 __check_assert_ok3
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01:4bb0 _print_sl_data31
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01:4bb5 _print_sl_out31
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01:4bb7 __check_assert_skip3
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01:4bbf _print_sl_data32
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01:4bc7 _print_sl_out32
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01:4bc7 __check_assert_out3
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01:4bd2 _print_sl_data33
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01:4bd5 _print_sl_out33
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01:4be1 _print_sl_data34
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01:4be3 _print_sl_out34
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01:4beb _print_sl_data35
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01:4bee _print_sl_out35
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01:4bf8 __check_assert_fail4
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01:4c03 _print_sl_data36
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01:4c06 _print_sl_out36
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01:4c09 __check_assert_ok4
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01:4c11 _print_sl_data37
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01:4c16 _print_sl_out37
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01:4c18 __check_assert_skip4
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01:4c20 _print_sl_data38
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01:4c28 _print_sl_out38
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01:4c28 __check_assert_out4
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01:4c34 _print_sl_data39
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01:4c36 _print_sl_out39
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01:4c3e _print_sl_data40
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01:4c41 _print_sl_out40
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01:4c4b __check_assert_fail5
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01:4c56 _print_sl_data41
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01:4c59 _print_sl_out41
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01:4c5c __check_assert_ok5
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01:4c64 _print_sl_data42
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01:4c69 _print_sl_out42
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01:4c6b __check_assert_skip5
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01:4c73 _print_sl_data43
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01:4c7b _print_sl_out43
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01:4c7b __check_assert_out5
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01:4c86 _print_sl_data44
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01:4c89 _print_sl_out44
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01:4c95 _print_sl_data45
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01:4c97 _print_sl_out45
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01:4c9f _print_sl_data46
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01:4ca2 _print_sl_out46
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01:4cac __check_assert_fail6
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01:4cb7 _print_sl_data47
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01:4cba _print_sl_out47
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01:4cbd __check_assert_ok6
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01:4cc5 _print_sl_data48
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01:4cca _print_sl_out48
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01:4ccc __check_assert_skip6
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01:4cd4 _print_sl_data49
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01:4cdc _print_sl_out49
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01:4cdc __check_assert_out6
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01:4ce8 _print_sl_data50
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01:4cea _print_sl_out50
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01:4cf2 _print_sl_data51
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01:4cf5 _print_sl_out51
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01:4cff __check_assert_fail7
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01:4d0a _print_sl_data52
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01:4d0d _print_sl_out52
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01:4d10 __check_assert_ok7
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01:4d18 _print_sl_data53
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01:4d1d _print_sl_out53
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01:4d1f __check_assert_skip7
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01:4d27 _print_sl_data54
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01:4d2f _print_sl_out54
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01:4d2f __check_assert_out7
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00:016b fail
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00:017f _wait_ly_4
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00:0185 _wait_ly_5
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00:019b _print_results_halt_1
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00:019e _fail_cb
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00:01a6 _print_sl_data55
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00:01b2 _print_sl_out55
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00:01c2 _print_sl_data56
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00:01ce _print_sl_out56
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00:01d8 _print_sl_data57
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00:01e4 _print_sl_out57
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00:01ef _print_sl_data58
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00:01f5 _print_sl_out58
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00:0208 _print_sl_data59
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00:0215 _print_sl_out59
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00:0225 _print_sl_data60
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00:0232 _print_sl_out60
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00:0242 _print_sl_data61
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00:024f _print_sl_out61
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00:025a c000_functions_start
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00:025a run_test_suite
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00:0284 _wait_ly_6
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00:028a _wait_ly_7
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00:02a0 _print_results_halt_2
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00:02a3 _test_ok_cb_0
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00:02ab _print_sl_data62
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00:02b3 _print_sl_out62
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00:02b6 run_tests
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00:02c4 run_test_cases
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00:02d2 test_case
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00:02ef restore_mbc1
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00:02f8 switch_bank
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00:0309 fetch_expected_value
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00:0328 c000_functions_end
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00:0328 expected_banks
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