mirror of https://github.com/mgba-emu/mgba.git
657 lines
21 KiB
C
657 lines
21 KiB
C
/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include "memory.h"
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#include "core/interface.h"
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#include "gb/gb.h"
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#include "gb/io.h"
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#include "gb/mbc.h"
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#include "gb/serialize.h"
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#include "util/memory.h"
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mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory");
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static void _pristineCow(struct GB* gba);
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static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
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if (UNLIKELY(address > cpu->memory.activeRegionEnd)) {
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cpu->memory.setActiveRegion(cpu, address);
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return cpu->memory.cpuLoad8(cpu, address);
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}
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return cpu->memory.activeRegion[address & cpu->memory.activeMask];
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}
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static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
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struct GB* gb = (struct GB*) cpu->master;
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struct GBMemory* memory = &gb->memory;
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switch (address >> 12) {
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case GB_REGION_CART_BANK0:
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case GB_REGION_CART_BANK0 + 1:
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case GB_REGION_CART_BANK0 + 2:
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case GB_REGION_CART_BANK0 + 3:
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cpu->memory.cpuLoad8 = GBFastLoad8;
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cpu->memory.activeRegion = memory->romBase;
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cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
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cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
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break;
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case GB_REGION_CART_BANK1:
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case GB_REGION_CART_BANK1 + 1:
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case GB_REGION_CART_BANK1 + 2:
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case GB_REGION_CART_BANK1 + 3:
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cpu->memory.cpuLoad8 = GBFastLoad8;
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cpu->memory.activeRegion = memory->romBank;
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cpu->memory.activeRegionEnd = GB_BASE_VRAM;
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cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
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break;
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default:
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cpu->memory.cpuLoad8 = GBLoad8;
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break;
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}
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}
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static void _GBMemoryDMAService(struct GB* gb);
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static void _GBMemoryHDMAService(struct GB* gb);
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void GBMemoryInit(struct GB* gb) {
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struct LR35902Core* cpu = gb->cpu;
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cpu->memory.cpuLoad8 = GBLoad8;
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cpu->memory.load8 = GBLoad8;
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cpu->memory.store8 = GBStore8;
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cpu->memory.setActiveRegion = GBSetActiveRegion;
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gb->memory.wram = 0;
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gb->memory.wramBank = 0;
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gb->memory.rom = 0;
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gb->memory.romBank = 0;
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gb->memory.romSize = 0;
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gb->memory.sram = 0;
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gb->memory.mbcType = GB_MBC_AUTODETECT;
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gb->memory.mbc = 0;
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gb->memory.rtc = NULL;
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GBIOInit(gb);
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}
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void GBMemoryDeinit(struct GB* gb) {
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mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
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if (gb->memory.rom) {
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mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
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}
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}
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void GBMemoryReset(struct GB* gb) {
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if (gb->memory.wram) {
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mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
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}
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gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
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if (gb->model >= GB_MODEL_CGB) {
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uint32_t* base = (uint32_t*) gb->memory.wram;
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size_t i;
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uint32_t pattern = 0;
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for (i = 0; i < GB_SIZE_WORKING_RAM / 4; i += 4) {
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if ((i & 0x1FF) == 0) {
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pattern = ~pattern;
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}
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base[i + 0] = pattern;
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base[i + 1] = pattern;
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base[i + 2] = ~pattern;
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base[i + 3] = ~pattern;
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}
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}
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GBMemorySwitchWramBank(&gb->memory, 1);
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gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
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gb->memory.currentBank = 1;
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gb->memory.sramCurrentBank = 0;
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gb->memory.ime = false;
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gb->memory.ie = 0;
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gb->memory.dmaNext = INT_MAX;
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gb->memory.dmaRemaining = 0;
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gb->memory.dmaSource = 0;
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gb->memory.dmaDest = 0;
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gb->memory.hdmaNext = INT_MAX;
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gb->memory.hdmaRemaining = 0;
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gb->memory.hdmaSource = 0;
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gb->memory.hdmaDest = 0;
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gb->memory.isHdma = false;
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gb->memory.sramAccess = false;
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gb->memory.rtcAccess = false;
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gb->memory.activeRtcReg = 0;
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gb->memory.rtcLatched = false;
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memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
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memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
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memset(&gb->memory.mbcState, 0, sizeof(gb->memory.mbcState));
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GBMBCInit(gb);
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gb->memory.sramBank = gb->memory.sram;
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if (!gb->memory.wram) {
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GBMemoryDeinit(gb);
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}
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}
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void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
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bank &= 7;
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if (!bank) {
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bank = 1;
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}
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memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
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memory->wramCurrentBank = bank;
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}
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uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
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struct GB* gb = (struct GB*) cpu->master;
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struct GBMemory* memory = &gb->memory;
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switch (address >> 12) {
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case GB_REGION_CART_BANK0:
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case GB_REGION_CART_BANK0 + 1:
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case GB_REGION_CART_BANK0 + 2:
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case GB_REGION_CART_BANK0 + 3:
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return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
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case GB_REGION_CART_BANK1:
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case GB_REGION_CART_BANK1 + 1:
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case GB_REGION_CART_BANK1 + 2:
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case GB_REGION_CART_BANK1 + 3:
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return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
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case GB_REGION_VRAM:
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case GB_REGION_VRAM + 1:
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return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
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case GB_REGION_EXTERNAL_RAM:
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case GB_REGION_EXTERNAL_RAM + 1:
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if (memory->rtcAccess) {
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return memory->rtcRegs[memory->activeRtcReg];
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} else if (memory->sramAccess) {
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return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
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} else if (memory->mbcType == GB_MBC7) {
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return GBMBC7Read(memory, address);
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} else if (memory->mbcType == GB_HuC3) {
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return 0x01; // TODO: Is this supposed to be the current SRAM bank?
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}
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return 0xFF;
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case GB_REGION_WORKING_RAM_BANK0:
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case GB_REGION_WORKING_RAM_BANK0 + 2:
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return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
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case GB_REGION_WORKING_RAM_BANK1:
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return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
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default:
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if (address < GB_BASE_OAM) {
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return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
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}
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if (address < GB_BASE_UNUSABLE) {
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if (gb->video.mode < 2) {
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return gb->video.oam.raw[address & 0xFF];
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}
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return 0xFF;
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}
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if (address < GB_BASE_IO) {
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mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
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return 0xFF;
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}
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if (address < GB_BASE_HRAM) {
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return GBIORead(gb, address & (GB_SIZE_IO - 1));
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}
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if (address < GB_BASE_IE) {
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return memory->hram[address & GB_SIZE_HRAM];
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}
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return GBIORead(gb, REG_IE);
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}
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}
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void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
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struct GB* gb = (struct GB*) cpu->master;
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struct GBMemory* memory = &gb->memory;
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switch (address >> 12) {
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case GB_REGION_CART_BANK0:
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case GB_REGION_CART_BANK0 + 1:
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case GB_REGION_CART_BANK0 + 2:
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case GB_REGION_CART_BANK0 + 3:
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case GB_REGION_CART_BANK1:
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case GB_REGION_CART_BANK1 + 1:
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case GB_REGION_CART_BANK1 + 2:
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case GB_REGION_CART_BANK1 + 3:
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memory->mbc(gb, address, value);
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cpu->memory.setActiveRegion(cpu, cpu->pc);
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return;
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case GB_REGION_VRAM:
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case GB_REGION_VRAM + 1:
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// TODO: Block access in wrong modes
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gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
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return;
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case GB_REGION_EXTERNAL_RAM:
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case GB_REGION_EXTERNAL_RAM + 1:
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if (memory->rtcAccess) {
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memory->rtcRegs[memory->activeRtcReg] = value;
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} else if (memory->sramAccess) {
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memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
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} else if (memory->mbcType == GB_MBC7) {
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GBMBC7Write(memory, address, value);
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}
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gb->sramDirty |= GB_SRAM_DIRT_NEW;
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return;
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case GB_REGION_WORKING_RAM_BANK0:
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case GB_REGION_WORKING_RAM_BANK0 + 2:
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memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
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return;
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case GB_REGION_WORKING_RAM_BANK1:
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memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
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return;
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default:
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if (address < GB_BASE_OAM) {
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memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
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} else if (address < GB_BASE_UNUSABLE) {
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if (gb->video.mode < 2) {
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gb->video.oam.raw[address & 0xFF] = value;
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}
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} else if (address < GB_BASE_IO) {
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mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
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} else if (address < GB_BASE_HRAM) {
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GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
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} else if (address < GB_BASE_IE) {
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memory->hram[address & GB_SIZE_HRAM] = value;
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} else {
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GBIOWrite(gb, REG_IE, value);
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}
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}
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}
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uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment) {
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struct GB* gb = (struct GB*) cpu->master;
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struct GBMemory* memory = &gb->memory;
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switch (address >> 12) {
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case GB_REGION_CART_BANK0:
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case GB_REGION_CART_BANK0 + 1:
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case GB_REGION_CART_BANK0 + 2:
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case GB_REGION_CART_BANK0 + 3:
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return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
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case GB_REGION_CART_BANK1:
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case GB_REGION_CART_BANK1 + 1:
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case GB_REGION_CART_BANK1 + 2:
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case GB_REGION_CART_BANK1 + 3:
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if (segment < 0) {
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return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
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} else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
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return memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
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} else {
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return 0xFF;
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}
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case GB_REGION_VRAM:
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case GB_REGION_VRAM + 1:
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if (segment < 0) {
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return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
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} else if (segment < 2) {
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return gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment *GB_SIZE_VRAM_BANK0];
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} else {
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return 0xFF;
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}
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case GB_REGION_EXTERNAL_RAM:
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case GB_REGION_EXTERNAL_RAM + 1:
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if (memory->rtcAccess) {
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return memory->rtcRegs[memory->activeRtcReg];
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} else if (memory->sramAccess) {
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if (segment < 0) {
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return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
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} else if ((size_t) segment * GB_SIZE_EXTERNAL_RAM < gb->sramSize) {
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return memory->sram[(address & (GB_SIZE_EXTERNAL_RAM - 1)) + segment *GB_SIZE_EXTERNAL_RAM];
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} else {
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return 0xFF;
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}
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} else if (memory->mbcType == GB_MBC7) {
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return GBMBC7Read(memory, address);
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} else if (memory->mbcType == GB_HuC3) {
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return 0x01; // TODO: Is this supposed to be the current SRAM bank?
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}
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return 0xFF;
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case GB_REGION_WORKING_RAM_BANK0:
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case GB_REGION_WORKING_RAM_BANK0 + 2:
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return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
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case GB_REGION_WORKING_RAM_BANK1:
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if (segment < 0) {
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return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
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} else if (segment < 8) {
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return memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment *GB_SIZE_WORKING_RAM_BANK0];
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} else {
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return 0xFF;
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}
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default:
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if (address < GB_BASE_OAM) {
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return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
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}
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if (address < GB_BASE_UNUSABLE) {
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if (gb->video.mode < 2) {
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return gb->video.oam.raw[address & 0xFF];
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}
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return 0xFF;
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}
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if (address < GB_BASE_IO) {
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mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
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return 0xFF;
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}
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if (address < GB_BASE_HRAM) {
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return GBIORead(gb, address & (GB_SIZE_IO - 1));
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}
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if (address < GB_BASE_IE) {
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return memory->hram[address & GB_SIZE_HRAM];
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}
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return GBIORead(gb, REG_IE);
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}
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}
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int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles) {
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int nextEvent = INT_MAX;
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if (gb->memory.dmaRemaining) {
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gb->memory.dmaNext -= cycles;
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if (gb->memory.dmaNext <= 0) {
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_GBMemoryDMAService(gb);
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}
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nextEvent = gb->memory.dmaNext;
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}
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if (gb->memory.hdmaRemaining) {
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gb->memory.hdmaNext -= cycles;
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if (gb->memory.hdmaNext <= 0) {
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_GBMemoryHDMAService(gb);
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}
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if (gb->memory.hdmaNext < nextEvent) {
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nextEvent = gb->memory.hdmaNext;
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}
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}
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return nextEvent;
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}
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void GBMemoryDMA(struct GB* gb, uint16_t base) {
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if (base > 0xF100) {
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return;
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}
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gb->cpu->memory.store8 = GBDMAStore8;
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gb->cpu->memory.load8 = GBDMALoad8;
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gb->cpu->memory.cpuLoad8 = GBDMALoad8;
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gb->memory.dmaNext = gb->cpu->cycles + 8;
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if (gb->memory.dmaNext < gb->cpu->nextEvent) {
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gb->cpu->nextEvent = gb->memory.dmaNext;
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}
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gb->memory.dmaSource = base;
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gb->memory.dmaDest = 0;
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gb->memory.dmaRemaining = 0xA0;
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}
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void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
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gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
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gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
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gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
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gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
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gb->memory.hdmaSource &= 0xFFF0;
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if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
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mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
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return;
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}
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gb->memory.hdmaDest &= 0x1FF0;
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gb->memory.hdmaDest |= 0x8000;
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bool wasHdma = gb->memory.isHdma;
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gb->memory.isHdma = value & 0x80;
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if (!wasHdma && !gb->memory.isHdma) {
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gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
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gb->memory.hdmaNext = gb->cpu->cycles;
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gb->cpu->nextEvent = gb->cpu->cycles;
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}
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}
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void _GBMemoryDMAService(struct GB* gb) {
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uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
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// TODO: Can DMA write OAM during modes 2-3?
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gb->video.oam.raw[gb->memory.dmaDest] = b;
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++gb->memory.dmaSource;
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++gb->memory.dmaDest;
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--gb->memory.dmaRemaining;
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if (gb->memory.dmaRemaining) {
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gb->memory.dmaNext += 4;
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} else {
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gb->memory.dmaNext = INT_MAX;
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gb->cpu->memory.store8 = GBStore8;
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gb->cpu->memory.load8 = GBLoad8;
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}
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}
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void _GBMemoryHDMAService(struct GB* gb) {
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uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
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gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
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++gb->memory.hdmaSource;
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++gb->memory.hdmaDest;
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--gb->memory.hdmaRemaining;
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gb->cpu->cycles += 2;
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if (gb->memory.hdmaRemaining) {
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gb->memory.hdmaNext += 2;
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} else {
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gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
|
|
gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
|
|
gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
|
|
gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
|
|
if (gb->memory.isHdma) {
|
|
--gb->memory.io[REG_HDMA5];
|
|
if (gb->memory.io[REG_HDMA5] == 0xFF) {
|
|
gb->memory.isHdma = false;
|
|
}
|
|
} else {
|
|
gb->memory.io[REG_HDMA5] |= 0x80;
|
|
}
|
|
}
|
|
}
|
|
|
|
struct OAMBlock {
|
|
uint16_t low;
|
|
uint16_t high;
|
|
};
|
|
|
|
static const struct OAMBlock _oamBlockDMG[] = {
|
|
{ 0xA000, 0xFE00 },
|
|
{ 0xA000, 0xFE00 },
|
|
{ 0xA000, 0xFE00 },
|
|
{ 0xA000, 0xFE00 },
|
|
{ 0x8000, 0xA000 },
|
|
{ 0xA000, 0xFE00 },
|
|
{ 0xA000, 0xFE00 },
|
|
{ 0xA000, 0xFE00 },
|
|
};
|
|
|
|
static const struct OAMBlock _oamBlockCGB[] = {
|
|
{ 0xA000, 0xC000 },
|
|
{ 0xA000, 0xC000 },
|
|
{ 0xA000, 0xC000 },
|
|
{ 0xA000, 0xC000 },
|
|
{ 0x8000, 0xA000 },
|
|
{ 0xA000, 0xC000 },
|
|
{ 0xC000, 0xFE00 },
|
|
{ 0xA000, 0xC000 },
|
|
};
|
|
|
|
uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address) {
|
|
struct GB* gb = (struct GB*) cpu->master;
|
|
struct GBMemory* memory = &gb->memory;
|
|
const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
|
|
block = &block[memory->dmaSource >> 13];
|
|
if (address >= block->low && address < block->high) {
|
|
return 0xFF;
|
|
}
|
|
if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
|
|
return 0xFF;
|
|
}
|
|
return GBLoad8(cpu, address);
|
|
}
|
|
|
|
void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
|
|
struct GB* gb = (struct GB*) cpu->master;
|
|
struct GBMemory* memory = &gb->memory;
|
|
const struct OAMBlock* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
|
|
block = &block[memory->dmaSource >> 13];
|
|
if (address >= block->low && address < block->high) {
|
|
return;
|
|
}
|
|
if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
|
|
return;
|
|
}
|
|
GBStore8(cpu, address, value);
|
|
}
|
|
|
|
void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment) {
|
|
struct GB* gb = (struct GB*) cpu->master;
|
|
struct GBMemory* memory = &gb->memory;
|
|
int8_t oldValue = -1;
|
|
|
|
switch (address >> 12) {
|
|
case GB_REGION_CART_BANK0:
|
|
case GB_REGION_CART_BANK0 + 1:
|
|
case GB_REGION_CART_BANK0 + 2:
|
|
case GB_REGION_CART_BANK0 + 3:
|
|
_pristineCow(gb);
|
|
oldValue = memory->rom[address & (GB_SIZE_CART_BANK0 - 1)];
|
|
memory->rom[address & (GB_SIZE_CART_BANK0 - 1)] = value;
|
|
break;
|
|
case GB_REGION_CART_BANK1:
|
|
case GB_REGION_CART_BANK1 + 1:
|
|
case GB_REGION_CART_BANK1 + 2:
|
|
case GB_REGION_CART_BANK1 + 3:
|
|
_pristineCow(gb);
|
|
if (segment < 0) {
|
|
oldValue = memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
|
|
memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)] = value;
|
|
} else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
|
|
oldValue = memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
|
|
memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0] = value;
|
|
} else {
|
|
return;
|
|
}
|
|
break;
|
|
case GB_REGION_VRAM:
|
|
case GB_REGION_VRAM + 1:
|
|
if (segment < 0) {
|
|
oldValue = gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
|
|
gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
|
|
} else if (segment < 2) {
|
|
oldValue = gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0];
|
|
gb->video.vramBank[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0] = value;
|
|
} else {
|
|
return;
|
|
}
|
|
break;
|
|
case GB_REGION_EXTERNAL_RAM:
|
|
case GB_REGION_EXTERNAL_RAM + 1:
|
|
mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
|
|
return;
|
|
case GB_REGION_WORKING_RAM_BANK0:
|
|
case GB_REGION_WORKING_RAM_BANK0 + 2:
|
|
oldValue = memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
|
|
memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
|
|
break;
|
|
case GB_REGION_WORKING_RAM_BANK1:
|
|
if (segment < 0) {
|
|
oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
|
|
memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
|
|
} else if (segment < 8) {
|
|
oldValue = memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0];
|
|
memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0] = value;
|
|
} else {
|
|
return;
|
|
}
|
|
break;
|
|
default:
|
|
if (address < GB_BASE_OAM) {
|
|
oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
|
|
memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
|
|
} else if (address < GB_BASE_UNUSABLE) {
|
|
oldValue = gb->video.oam.raw[address & 0xFF];
|
|
gb->video.oam.raw[address & 0xFF] = value;
|
|
} else if (address < GB_BASE_HRAM) {
|
|
mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
|
|
return;
|
|
} else if (address < GB_BASE_IE) {
|
|
oldValue = memory->hram[address & GB_SIZE_HRAM];
|
|
memory->hram[address & GB_SIZE_HRAM] = value;
|
|
} else {
|
|
mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
|
|
return;
|
|
}
|
|
}
|
|
if (old) {
|
|
*old = oldValue;
|
|
}
|
|
}
|
|
|
|
void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state) {
|
|
const struct GBMemory* memory = &gb->memory;
|
|
memcpy(state->wram, memory->wram, GB_SIZE_WORKING_RAM);
|
|
memcpy(state->hram, memory->hram, GB_SIZE_HRAM);
|
|
STORE_16LE(memory->currentBank, 0, &state->memory.currentBank);
|
|
state->memory.wramCurrentBank = memory->wramCurrentBank;
|
|
state->memory.sramCurrentBank = memory->sramCurrentBank;
|
|
|
|
STORE_32LE(memory->dmaNext, 0, &state->memory.dmaNext);
|
|
STORE_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
|
|
STORE_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
|
|
|
|
STORE_32LE(memory->hdmaNext, 0, &state->memory.hdmaNext);
|
|
STORE_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
|
|
STORE_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
|
|
|
|
STORE_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
|
|
state->memory.dmaRemaining = memory->dmaRemaining;
|
|
memcpy(state->memory.rtcRegs, memory->rtcRegs, sizeof(state->memory.rtcRegs));
|
|
|
|
GBSerializedMemoryFlags flags = 0;
|
|
flags = GBSerializedMemoryFlagsSetSramAccess(flags, memory->sramAccess);
|
|
flags = GBSerializedMemoryFlagsSetRtcAccess(flags, memory->rtcAccess);
|
|
flags = GBSerializedMemoryFlagsSetRtcLatched(flags, memory->rtcLatched);
|
|
flags = GBSerializedMemoryFlagsSetIme(flags, memory->ime);
|
|
flags = GBSerializedMemoryFlagsSetIsHdma(flags, memory->isHdma);
|
|
flags = GBSerializedMemoryFlagsSetActiveRtcReg(flags, memory->activeRtcReg);
|
|
STORE_16LE(flags, 0, &state->memory.flags);
|
|
}
|
|
|
|
void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state) {
|
|
struct GBMemory* memory = &gb->memory;
|
|
memcpy(memory->wram, state->wram, GB_SIZE_WORKING_RAM);
|
|
memcpy(memory->hram, state->hram, GB_SIZE_HRAM);
|
|
LOAD_16LE(memory->currentBank, 0, &state->memory.currentBank);
|
|
memory->wramCurrentBank = state->memory.wramCurrentBank;
|
|
memory->sramCurrentBank = state->memory.sramCurrentBank;
|
|
|
|
GBMBCSwitchBank(memory, memory->currentBank);
|
|
GBMemorySwitchWramBank(memory, memory->wramCurrentBank);
|
|
GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
|
|
|
|
LOAD_32LE(memory->dmaNext, 0, &state->memory.dmaNext);
|
|
LOAD_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
|
|
LOAD_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
|
|
|
|
LOAD_32LE(memory->hdmaNext, 0, &state->memory.hdmaNext);
|
|
LOAD_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
|
|
LOAD_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
|
|
|
|
LOAD_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
|
|
memory->dmaRemaining = state->memory.dmaRemaining;
|
|
memcpy(memory->rtcRegs, state->memory.rtcRegs, sizeof(state->memory.rtcRegs));
|
|
|
|
GBSerializedMemoryFlags flags;
|
|
LOAD_16LE(flags, 0, &state->memory.flags);
|
|
memory->sramAccess = GBSerializedMemoryFlagsGetSramAccess(flags);
|
|
memory->rtcAccess = GBSerializedMemoryFlagsGetRtcAccess(flags);
|
|
memory->rtcLatched = GBSerializedMemoryFlagsGetRtcLatched(flags);
|
|
memory->ime = GBSerializedMemoryFlagsGetIme(flags);
|
|
memory->isHdma = GBSerializedMemoryFlagsGetIsHdma(flags);
|
|
memory->activeRtcReg = GBSerializedMemoryFlagsGetActiveRtcReg(flags);
|
|
}
|
|
|
|
void _pristineCow(struct GB* gb) {
|
|
if (gb->memory.rom != gb->pristineRom) {
|
|
return;
|
|
}
|
|
gb->memory.rom = anonymousMemoryMap(GB_SIZE_CART_MAX);
|
|
memcpy(gb->memory.rom, gb->pristineRom, gb->memory.romSize);
|
|
memset(((uint8_t*) gb->memory.rom) + gb->memory.romSize, 0xFF, GB_SIZE_CART_MAX - gb->memory.romSize);
|
|
GBMBCSwitchBank(&gb->memory, gb->memory.currentBank);
|
|
}
|