; this file was created with wlalink by ville helin . ; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/stat_irq_blocking.gb". [labels] 01:4940 clear_vram 01:48ff disable_lcd_safe 01:4905 disable_lcd_safe@wait_ly_0 01:4954 memcpy 01:495d memset 01:491d print_hex4 01:494a print_hex8 01:496d print_inline_string 01:4929 print_load_font 01:4935 print_newline 01:47f0 print_reg_dump 01:4966 print_string 01:4875 quit 01:488a quit@cb_return 01:488f quit@wait_ly_1 01:4895 quit@wait_ly_2 01:489b quit@wait_ly_3 01:48a1 quit@wait_ly_4 01:48ab quit@success 01:48d2 quit@failure 01:48e7 quit@halt 01:48e8 quit@halt_execution_0 01:48eb reset_screen 01:490e serial_send_byte 01:4000 font 00:ff80 v_regs_save 00:ff80 v_regs_save.reg_f 00:ff81 v_regs_save.reg_a 00:ff82 v_regs_save.reg_c 00:ff83 v_regs_save.reg_b 00:ff84 v_regs_save.reg_e 00:ff85 v_regs_save.reg_d 00:ff86 v_regs_save.reg_l 00:ff87 v_regs_save.reg_h 00:ff88 v_regs_flags 00:ff89 v_regs_assert 00:ff89 v_regs_assert.reg_f 00:ff8a v_regs_assert.reg_a 00:ff8b v_regs_assert.reg_c 00:ff8c v_regs_assert.reg_b 00:ff8d v_regs_assert.reg_e 00:ff8e v_regs_assert.reg_d 00:ff8f v_regs_assert.reg_l 00:ff90 v_regs_assert.reg_h 00:0150 main 00:0151 test_round1 00:0156 test_round1@wait_ly_5 00:015c test_round1@wait_ly_6 00:016b fail_round1 00:0173 fail_round1@quit_inline_1 00:018e test_round2 00:0198 ly_iteration 00:01ae finish_round2 00:01b6 finish_round2@quit_inline_2 00:01c7 fail_round2 00:01ec fail_round2@quit_inline_3 [definitions] 0000000a _sizeof_clear_vram 0000000f _sizeof_disable_lcd_safe 00000009 _sizeof_memcpy 00000009 _sizeof_memset 0000000c _sizeof_print_hex4 0000000a _sizeof_print_hex8 00000006 _sizeof_print_inline_string 0000000c _sizeof_print_load_font 0000000b _sizeof_print_newline 00000085 _sizeof_print_reg_dump 00000007 _sizeof_print_string 00000076 _sizeof_quit 00000014 _sizeof_reset_screen 0000000f _sizeof_serial_send_byte 000007f0 _sizeof_font 00000008 _sizeof_v_regs_save 00000001 _sizeof_v_regs_save.reg_f 00000001 _sizeof_v_regs_save.reg_a 00000001 _sizeof_v_regs_save.reg_c 00000001 _sizeof_v_regs_save.reg_b 00000001 _sizeof_v_regs_save.reg_e 00000001 _sizeof_v_regs_save.reg_d 00000001 _sizeof_v_regs_save.reg_l 00000001 _sizeof_v_regs_save.reg_h 00000001 _sizeof_v_regs_flags 00000008 _sizeof_v_regs_assert 00000001 _sizeof_v_regs_assert.reg_f 00000001 _sizeof_v_regs_assert.reg_a 00000001 _sizeof_v_regs_assert.reg_c 00000001 _sizeof_v_regs_assert.reg_b 00000001 _sizeof_v_regs_assert.reg_e 00000001 _sizeof_v_regs_assert.reg_d 00000001 _sizeof_v_regs_assert.reg_l 00000001 _sizeof_v_regs_assert.reg_h 00000001 _sizeof_main 0000001a _sizeof_test_round1 00000023 _sizeof_fail_round1 0000000a _sizeof_test_round2 00000016 _sizeof_ly_iteration 00000019 _sizeof_finish_round2