; this file was created with wlalink by ville helin <vhelin@iki.fi>.
; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg.gb".

[labels]
0001:4bf2 print_load_font
0001:4bff print_string
0001:4c09 print_a
0001:4c13 print_newline
0001:4c1e print_digit
0001:4c2b print_regs
0001:4c34 _print_sl_data0
0001:4c3a _print_sl_out0
0001:4c47 _print_sl_data1
0001:4c4d _print_sl_out1
0001:4c5f _print_sl_data2
0001:4c65 _print_sl_out2
0001:4c72 _print_sl_data3
0001:4c78 _print_sl_out3
0001:4c8a _print_sl_data4
0001:4c90 _print_sl_out4
0001:4c9d _print_sl_data5
0001:4ca3 _print_sl_out5
0001:4cb5 _print_sl_data6
0001:4cbb _print_sl_out6
0001:4cc8 _print_sl_data7
0001:4cce _print_sl_out7
0001:4000 font
0000:c000 regs_save
0000:c000 regs_save.f
0000:c001 regs_save.a
0000:c002 regs_save.c
0000:c003 regs_save.b
0000:c004 regs_save.e
0000:c005 regs_save.d
0000:c006 regs_save.l
0000:c007 regs_save.h
0000:c008 regs_flags
0000:c009 regs_assert
0000:c009 regs_assert.f
0000:c00a regs_assert.a
0000:c00b regs_assert.c
0000:c00c regs_assert.b
0000:c00d regs_assert.e
0000:c00e regs_assert.d
0000:c00f regs_assert.l
0000:c010 regs_assert.h
0000:c011 memdump_len
0000:c012 memdump_addr
0001:47f0 memcpy
0001:47f9 memset
0001:4802 clear_vram
0001:480d reset_screen
0001:481a process_results
0001:481f _wait_ly_0
0001:4825 _wait_ly_1
0001:4841 _wait_ly_2
0001:4847 _wait_ly_3
0001:4860 _process_results_cb
0001:486b _print_sl_data8
0001:4875 _print_sl_out8
0001:488f _print_sl_data9
0001:489a _print_sl_out9
0001:48b2 _print_sl_data10
0001:48be _print_sl_out10
0001:48bf dump_mem
0001:48cf _wait_ly_4
0001:48d5 _wait_ly_5
0001:48f1 _dump_mem_line
0001:491b _check_asserts
0001:4929 _print_sl_data11
0001:492c _print_sl_out11
0001:4938 _print_sl_data12
0001:493a _print_sl_out12
0001:4942 _print_sl_data13
0001:4945 _print_sl_out13
0001:494f __check_assert_fail0
0001:495a _print_sl_data14
0001:495d _print_sl_out14
0001:4960 __check_assert_ok0
0001:4968 _print_sl_data15
0001:496d _print_sl_out15
0001:496f __check_assert_skip0
0001:4977 _print_sl_data16
0001:497f _print_sl_out16
0001:497f __check_assert_out0
0001:498b _print_sl_data17
0001:498d _print_sl_out17
0001:4995 _print_sl_data18
0001:4998 _print_sl_out18
0001:49a2 __check_assert_fail1
0001:49ad _print_sl_data19
0001:49b0 _print_sl_out19
0001:49b3 __check_assert_ok1
0001:49bb _print_sl_data20
0001:49c0 _print_sl_out20
0001:49c2 __check_assert_skip1
0001:49ca _print_sl_data21
0001:49d2 _print_sl_out21
0001:49d2 __check_assert_out1
0001:49dd _print_sl_data22
0001:49e0 _print_sl_out22
0001:49ec _print_sl_data23
0001:49ee _print_sl_out23
0001:49f6 _print_sl_data24
0001:49f9 _print_sl_out24
0001:4a03 __check_assert_fail2
0001:4a0e _print_sl_data25
0001:4a11 _print_sl_out25
0001:4a14 __check_assert_ok2
0001:4a1c _print_sl_data26
0001:4a21 _print_sl_out26
0001:4a23 __check_assert_skip2
0001:4a2b _print_sl_data27
0001:4a33 _print_sl_out27
0001:4a33 __check_assert_out2
0001:4a3f _print_sl_data28
0001:4a41 _print_sl_out28
0001:4a49 _print_sl_data29
0001:4a4c _print_sl_out29
0001:4a56 __check_assert_fail3
0001:4a61 _print_sl_data30
0001:4a64 _print_sl_out30
0001:4a67 __check_assert_ok3
0001:4a6f _print_sl_data31
0001:4a74 _print_sl_out31
0001:4a76 __check_assert_skip3
0001:4a7e _print_sl_data32
0001:4a86 _print_sl_out32
0001:4a86 __check_assert_out3
0001:4a91 _print_sl_data33
0001:4a94 _print_sl_out33
0001:4aa0 _print_sl_data34
0001:4aa2 _print_sl_out34
0001:4aaa _print_sl_data35
0001:4aad _print_sl_out35
0001:4ab7 __check_assert_fail4
0001:4ac2 _print_sl_data36
0001:4ac5 _print_sl_out36
0001:4ac8 __check_assert_ok4
0001:4ad0 _print_sl_data37
0001:4ad5 _print_sl_out37
0001:4ad7 __check_assert_skip4
0001:4adf _print_sl_data38
0001:4ae7 _print_sl_out38
0001:4ae7 __check_assert_out4
0001:4af3 _print_sl_data39
0001:4af5 _print_sl_out39
0001:4afd _print_sl_data40
0001:4b00 _print_sl_out40
0001:4b0a __check_assert_fail5
0001:4b15 _print_sl_data41
0001:4b18 _print_sl_out41
0001:4b1b __check_assert_ok5
0001:4b23 _print_sl_data42
0001:4b28 _print_sl_out42
0001:4b2a __check_assert_skip5
0001:4b32 _print_sl_data43
0001:4b3a _print_sl_out43
0001:4b3a __check_assert_out5
0001:4b45 _print_sl_data44
0001:4b48 _print_sl_out44
0001:4b54 _print_sl_data45
0001:4b56 _print_sl_out45
0001:4b5e _print_sl_data46
0001:4b61 _print_sl_out46
0001:4b6b __check_assert_fail6
0001:4b76 _print_sl_data47
0001:4b79 _print_sl_out47
0001:4b7c __check_assert_ok6
0001:4b84 _print_sl_data48
0001:4b89 _print_sl_out48
0001:4b8b __check_assert_skip6
0001:4b93 _print_sl_data49
0001:4b9b _print_sl_out49
0001:4b9b __check_assert_out6
0001:4ba7 _print_sl_data50
0001:4ba9 _print_sl_out50
0001:4bb1 _print_sl_data51
0001:4bb4 _print_sl_out51
0001:4bbe __check_assert_fail7
0001:4bc9 _print_sl_data52
0001:4bcc _print_sl_out52
0001:4bcf __check_assert_ok7
0001:4bd7 _print_sl_data53
0001:4bdc _print_sl_out53
0001:4bde __check_assert_skip7
0001:4be6 _print_sl_data54
0001:4bee _print_sl_out54
0001:4bee __check_assert_out7
0000:01d2 invalid_sp
0000:01d7 _wait_ly_6
0000:01dd _wait_ly_7
0000:01f9 _wait_ly_8
0000:01ff _wait_ly_9
0000:0218 _test_failure_cb_0
0000:0220 _print_sl_data55
0000:0231 _print_sl_out55
0000:c014 sp_save