; this file was created with wlalink by ville helin . ; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_8Mb.gb". [labels] 01:4c00 print_load_font 01:4c0d print_string 01:4c17 print_a 01:4c21 print_newline 01:4c2c print_digit 01:4c39 print_regs 01:4c42 _print_sl_data0 01:4c48 _print_sl_out0 01:4c55 _print_sl_data1 01:4c5b _print_sl_out1 01:4c6d _print_sl_data2 01:4c73 _print_sl_out2 01:4c80 _print_sl_data3 01:4c86 _print_sl_out3 01:4c98 _print_sl_data4 01:4c9e _print_sl_out4 01:4cab _print_sl_data5 01:4cb1 _print_sl_out5 01:4cc3 _print_sl_data6 01:4cc9 _print_sl_out6 01:4cd6 _print_sl_data7 01:4cdc _print_sl_out7 01:4001 font 00:c000 regs_save 00:c000 regs_save.f 00:c001 regs_save.a 00:c002 regs_save.c 00:c003 regs_save.b 00:c004 regs_save.e 00:c005 regs_save.d 00:c006 regs_save.l 00:c007 regs_save.h 00:c008 regs_flags 00:c009 regs_assert 00:c009 regs_assert.f 00:c00a regs_assert.a 00:c00b regs_assert.c 00:c00c regs_assert.b 00:c00d regs_assert.e 00:c00e regs_assert.d 00:c00f regs_assert.l 00:c010 regs_assert.h 00:c011 memdump_len 00:c012 memdump_addr 01:47f1 memcpy 01:47fa memset 01:4803 memcmp 01:4811 clear_vram 01:481b clear_oam 01:4825 disable_lcd_safe 01:482b _wait_ly_0 01:4831 _wait_ly_1 01:483a reset_screen 01:484e process_results 01:4862 _wait_ly_2 01:4868 _wait_ly_3 01:487e _print_results_halt_0 01:4881 _process_results_cb 01:488c _print_sl_data8 01:4896 _print_sl_out8 01:48b0 _print_sl_data9 01:48bb _print_sl_out9 01:48d3 _print_sl_data10 01:48df _print_sl_out10 01:48e0 dump_mem 01:48ff _dump_mem_line 01:4929 _check_asserts 01:4937 _print_sl_data11 01:493a _print_sl_out11 01:4946 _print_sl_data12 01:4948 _print_sl_out12 01:4950 _print_sl_data13 01:4953 _print_sl_out13 01:495d __check_assert_fail0 01:4968 _print_sl_data14 01:496b _print_sl_out14 01:496e __check_assert_ok0 01:4976 _print_sl_data15 01:497b _print_sl_out15 01:497d __check_assert_skip0 01:4985 _print_sl_data16 01:498d _print_sl_out16 01:498d __check_assert_out0 01:4999 _print_sl_data17 01:499b _print_sl_out17 01:49a3 _print_sl_data18 01:49a6 _print_sl_out18 01:49b0 __check_assert_fail1 01:49bb _print_sl_data19 01:49be _print_sl_out19 01:49c1 __check_assert_ok1 01:49c9 _print_sl_data20 01:49ce _print_sl_out20 01:49d0 __check_assert_skip1 01:49d8 _print_sl_data21 01:49e0 _print_sl_out21 01:49e0 __check_assert_out1 01:49eb _print_sl_data22 01:49ee _print_sl_out22 01:49fa _print_sl_data23 01:49fc _print_sl_out23 01:4a04 _print_sl_data24 01:4a07 _print_sl_out24 01:4a11 __check_assert_fail2 01:4a1c _print_sl_data25 01:4a1f _print_sl_out25 01:4a22 __check_assert_ok2 01:4a2a _print_sl_data26 01:4a2f _print_sl_out26 01:4a31 __check_assert_skip2 01:4a39 _print_sl_data27 01:4a41 _print_sl_out27 01:4a41 __check_assert_out2 01:4a4d _print_sl_data28 01:4a4f _print_sl_out28 01:4a57 _print_sl_data29 01:4a5a _print_sl_out29 01:4a64 __check_assert_fail3 01:4a6f _print_sl_data30 01:4a72 _print_sl_out30 01:4a75 __check_assert_ok3 01:4a7d _print_sl_data31 01:4a82 _print_sl_out31 01:4a84 __check_assert_skip3 01:4a8c _print_sl_data32 01:4a94 _print_sl_out32 01:4a94 __check_assert_out3 01:4a9f _print_sl_data33 01:4aa2 _print_sl_out33 01:4aae _print_sl_data34 01:4ab0 _print_sl_out34 01:4ab8 _print_sl_data35 01:4abb _print_sl_out35 01:4ac5 __check_assert_fail4 01:4ad0 _print_sl_data36 01:4ad3 _print_sl_out36 01:4ad6 __check_assert_ok4 01:4ade _print_sl_data37 01:4ae3 _print_sl_out37 01:4ae5 __check_assert_skip4 01:4aed _print_sl_data38 01:4af5 _print_sl_out38 01:4af5 __check_assert_out4 01:4b01 _print_sl_data39 01:4b03 _print_sl_out39 01:4b0b _print_sl_data40 01:4b0e _print_sl_out40 01:4b18 __check_assert_fail5 01:4b23 _print_sl_data41 01:4b26 _print_sl_out41 01:4b29 __check_assert_ok5 01:4b31 _print_sl_data42 01:4b36 _print_sl_out42 01:4b38 __check_assert_skip5 01:4b40 _print_sl_data43 01:4b48 _print_sl_out43 01:4b48 __check_assert_out5 01:4b53 _print_sl_data44 01:4b56 _print_sl_out44 01:4b62 _print_sl_data45 01:4b64 _print_sl_out45 01:4b6c _print_sl_data46 01:4b6f _print_sl_out46 01:4b79 __check_assert_fail6 01:4b84 _print_sl_data47 01:4b87 _print_sl_out47 01:4b8a __check_assert_ok6 01:4b92 _print_sl_data48 01:4b97 _print_sl_out48 01:4b99 __check_assert_skip6 01:4ba1 _print_sl_data49 01:4ba9 _print_sl_out49 01:4ba9 __check_assert_out6 01:4bb5 _print_sl_data50 01:4bb7 _print_sl_out50 01:4bbf _print_sl_data51 01:4bc2 _print_sl_out51 01:4bcc __check_assert_fail7 01:4bd7 _print_sl_data52 01:4bda _print_sl_out52 01:4bdd __check_assert_ok7 01:4be5 _print_sl_data53 01:4bea _print_sl_out53 01:4bec __check_assert_skip7 01:4bf4 _print_sl_data54 01:4bfc _print_sl_out54 01:4bfc __check_assert_out7 00:016b fail 00:017f _wait_ly_4 00:0185 _wait_ly_5 00:019b _print_results_halt_1 00:019e _fail_cb 00:01a6 _print_sl_data55 00:01b2 _print_sl_out55 00:01c2 _print_sl_data56 00:01ce _print_sl_out56 00:01d8 _print_sl_data57 00:01e4 _print_sl_out57 00:01ef _print_sl_data58 00:01f5 _print_sl_out58 00:0208 _print_sl_data59 00:0215 _print_sl_out59 00:0225 _print_sl_data60 00:0232 _print_sl_out60 00:0242 _print_sl_data61 00:024f _print_sl_out61 00:025a c000_functions_start 00:025a run_test_suite 00:0284 _wait_ly_6 00:028a _wait_ly_7 00:02a0 _print_results_halt_2 00:02a3 _test_ok_cb_0 00:02ab _print_sl_data62 00:02b3 _print_sl_out62 00:02b6 run_tests 00:02c4 run_test_cases 00:02d2 test_case 00:02ef restore_mbc1 00:02f8 switch_bank 00:0309 fetch_expected_value 00:0328 c000_functions_end 00:0328 expected_banks