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mgba
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7,848 Commits 36 Branches 38 Tags 63 MiB
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7848 Commits

Author SHA1 Message Date
Jeffrey Pfau cb48145ea3 Move main emulation into thread 2013-04-20 15:54:09 -07:00
Jeffrey Pfau ff03bcf0f0 Fix MidiKey2Freq 2013-04-20 14:46:53 -07:00
Jeffrey Pfau 18fae08450 Fix Load/store shifters 2013-04-20 14:21:42 -07:00
Jeffrey Pfau cd0f75c83f Implement MLA 2013-04-20 13:36:42 -07:00
Jeffrey Pfau bf54a68b0e Implement UMULL 2013-04-20 13:22:10 -07:00
Jeffrey Pfau 63e809550d Implement MidiKey2Freq 2013-04-20 03:01:50 -07:00
Jeffrey Pfau e272481ccd Implement LDR(2) 2013-04-20 02:57:20 -07:00
Jeffrey Pfau e83936152d Implement LZ77 decompression 2013-04-20 02:52:10 -07:00
Jeffrey Pfau cf9a7224a3 Init video memory from the dummy renderer 2013-04-20 02:51:40 -07:00
Jeffrey Pfau 1972e73bec Define memory regions 2013-04-19 23:34:26 -07:00
Jeffrey Pfau f72c195739 Labels for I/O regions in the switch statement 2013-04-19 23:04:01 -07:00
Jeffrey Pfau 5d81a4eb18 Remainder of timer infrastructure 2013-04-19 23:01:04 -07:00
Jeffrey Pfau 57dcbef030 Implement timers from GBA.js implementation 2013-04-19 22:26:44 -07:00
Jeffrey Pfau 6087ad8c5f Fix reading from DISPSTAT 2013-04-19 21:40:57 -07:00
Jeffrey Pfau adfd8f6872 Make sure if we reset the CPSR to the SPSR that we check if we get tossed into Thumb 2013-04-19 21:26:00 -07:00
Jeffrey Pfau 633a87269a Initialize cpu->privilegeMode 2013-04-19 21:09:00 -07:00
Jeffrey Pfau aa7ef287bc Squelch HLE BIOS warnings 2013-04-19 21:04:53 -07:00
Jeffrey Pfau 283a48613b Read/write REG_IF 2013-04-19 00:05:13 -07:00
Jeffrey Pfau 9b1f3c3c73 Init GBA I/O registers 2013-04-19 00:04:50 -07:00
Jeffrey Pfau 0ba7451e3a Install SIGINT signal handler for debugger 2013-04-18 01:52:46 -07:00
Jeffrey Pfau 0b468a9db8 Null-check that DebugVectors get generated 2013-04-18 01:39:51 -07:00
Jeffrey Pfau 5f1f6088bd Implement MUL 2013-04-18 01:35:48 -07:00
Jeffrey Pfau 783b2a3e09 Implement ADD(5) 2013-04-18 01:24:46 -07:00
Jeffrey Pfau 422961a2df 8-bit I/O reads 2013-04-18 01:19:57 -07:00
Jeffrey Pfau 97b669e4d1 Store vcount back in IO 2013-04-18 01:19:41 -07:00
Jeffrey Pfau 0048de2108 Fix addressing mode 3 immediate 2013-04-18 01:06:19 -07:00
Jeffrey Pfau b5cbd55718 Read back I/O memory when reading 32-bit 2013-04-18 00:58:42 -07:00
Jeffrey Pfau 1e1c8fd2dd Ensure that DMAs read back from I/O memory properly 2013-04-18 00:58:22 -07:00
Jeffrey Pfau 4f8c288f20 Ensure cpsr.t reads back out properly 2013-04-18 00:19:41 -07:00
Jeffrey Pfau ed48ab1c64 Fix storing SPSR 2013-04-18 00:15:45 -07:00
Jeffrey Pfau 062e09ccf5 Implement MSRI 2013-04-18 00:09:28 -07:00
Jeffrey Pfau fdf36f5820 Implement MRS 2013-04-18 00:06:48 -07:00
Jeffrey Pfau b3832205fc Fix some MRS/MSR encoding problems 2013-04-18 00:03:39 -07:00
Jeffrey Pfau 6608ae282c Ensure loads to PC work 2013-04-17 23:54:31 -07:00
Jeffrey Pfau cb03781a5b Implement LDM, STM 2013-04-17 23:44:35 -07:00
Jeffrey Pfau dd479ad907 Now include source for HLE BIOS, even without assembler script 2013-04-17 00:46:32 -07:00
Jeffrey Pfau 54fffb7fff Add HLE BIOS from GBA.js 2013-04-17 00:45:23 -07:00
Jeffrey Pfau 38b1c8d235 Make sure CPSR is updated for IRQ mode properly 2013-04-17 00:29:20 -07:00
Jeffrey Pfau f30b367c7e Make sure to rewrite active region data when jumping to IRQ handler 2013-04-17 00:24:00 -07:00
Jeffrey Pfau 45fcd0fcb5 Implement FastCpuSet 2013-04-16 23:52:53 -07:00
Jeffrey Pfau c143dec77d Fix ADD(4) and MOV(3) 2013-04-16 23:52:30 -07:00
Jeffrey Pfau 4b4914afb6 Implement MUL 2013-04-16 23:26:49 -07:00
Jeffrey Pfau 6b07dd33af Implement ASR(1) 2013-04-16 23:24:19 -07:00
Jeffrey Pfau 8c03c20019 Implement HALT 2013-04-16 23:14:16 -07:00
Jeffrey Pfau e88d177582 Copy GBA.js DMA implementation 2013-04-16 23:13:52 -07:00
Jeffrey Pfau 20622b6135 Copy some IRQ infrastructure from GBA.js 2013-04-16 19:44:16 -07:00
Jeffrey Pfau bc9d0690bb Clean up extra backslashes 2013-04-16 19:29:00 -07:00
Jeffrey Pfau 2d0c3bf275 Implement IRQs 2013-04-16 07:50:34 -07:00
Jeffrey Pfau 2da11dd523 Continue implementing IRQs 2013-04-16 07:42:20 -07:00
Jeffrey Pfau 4dd98f4c25 Remove typo struct member 2013-04-16 07:20:28 -07:00