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mgba
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8,579 Commits 36 Branches 39 Tags 67 MiB
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323 Commits

Author SHA1 Message Date
Jeffrey Pfau f90b01b95d Fix setting privilege mode when entering SVC 2013-10-14 22:32:52 -07:00
Jeffrey Pfau 09a0f95ed4 Actually use GBATestIRQ 2013-10-09 01:56:59 -07:00
Jeffrey Pfau c3a7d87214 Add missing variable 2013-10-09 00:44:44 -07:00
Jeffrey Pfau 3e3bb58ae5 Minor timing fixes 2013-10-08 02:10:43 -07:00
Jeffrey Pfau 25885e1e82 Invalid memory reads 2013-09-27 23:48:56 -07:00
Jeffrey Pfau 99769695d7 Fix ADCS C bit 2013-09-26 00:25:48 -07:00
Jeffrey Pfau 13a2289e25 Fix ADCS 2013-09-25 00:27:40 -07:00
Jeffrey Pfau 6b86cdf9ef LDM should force-align loads 2013-07-31 01:59:00 -07:00
Jeffrey Pfau 425056ca15 Ensure LDM does not write back incorrectly with register list overlaps 2013-07-27 03:02:52 -07:00
Jeffrey Pfau 9e578da5a1 Do register writeback in addressing mode 2 before actual load/store 2013-07-26 23:42:45 -07:00
Jeffrey Pfau 8b1eb01a96 Fix MUL, UMULL, UMLAL 2013-07-26 01:03:34 -07:00
Jeffrey Pfau 6321b1f827 Fix ARM_CARRY_FROM 2013-07-26 00:50:20 -07:00
Jeffrey Pfau a6d87bbfb9 Better cycle counting for STR 2013-05-11 18:01:16 -07:00
Jeffrey Pfau b6361cdfa9 Start LDM/STM timings 2013-05-11 17:05:57 -07:00
Jeffrey Pfau 013e322c0b Improved cycle counting for branches 2013-05-11 14:45:31 -07:00
Jeffrey Pfau f6592b17b8 Implement MUL timings 2013-05-11 14:35:10 -07:00
Jeffrey Pfau fc7aec557b Count cycles for load/store singles 2013-05-04 23:57:12 -07:00
Jeffrey Pfau 13a46429e2 Remove -Wno-unused and fix resulting errors 2013-05-02 00:35:32 -07:00
Jeffrey Pfau a635f4de4d Implement addressing mode 1 ASR register shift 2013-05-02 00:32:04 -07:00
Jeffrey Pfau 86c228f2e4 Implement SMLAL 2013-05-02 00:29:06 -07:00
Jeffrey Pfau 61c6b7186e Implement UMLAL 2013-05-01 23:11:00 -07:00
Jeffrey Pfau cd73c562ea Implement addressing mode 1 LSL/LSR with register 2013-05-01 23:08:22 -07:00
Jeffrey Pfau da489b90f8 Ensure shifter carry-out gets bits set right 2013-04-30 21:02:56 -07:00
Jeffrey Pfau 118c393d1b Fix addressing mode 2 register post-indexed 2013-04-30 02:43:12 -07:00
Jeffrey Pfau 337d4dc1e6 Implement addressing mode 1 ROR with register 2013-04-30 02:42:54 -07:00
Jeffrey Pfau e1963c6e60 Implement SMULL 2013-04-30 01:42:24 -07:00
Jeffrey Pfau 6450ce16b2 Fix LDR(3) 2013-04-28 01:33:45 -07:00
Jeffrey Pfau e86f7d79fb Clean up and fix conditions for CPSR V 2013-04-28 00:19:15 -07:00
Jeffrey Pfau 19f9b72c33 Fix CPSR C being written 2013-04-28 00:06:13 -07:00
Jeffrey Pfau 682684cb6d Output MUL into the right register 2013-04-27 23:44:33 -07:00
Jeffrey Pfau 2c8786ae4c Use LE instead of GE where appropriate 2013-04-27 23:44:17 -07:00
Jeffrey Pfau 2e78381e55 Implement SWI 2013-04-27 02:56:34 -07:00
Jeffrey Pfau 6c44cf8dfc Implement BL 2013-04-27 02:54:16 -07:00
Jeffrey Pfau 21b9222357 Fix entering SWI mode 2013-04-27 02:50:35 -07:00
Jeffrey Pfau bd9714b540 Implement STR(2)/STRH(2) 2013-04-27 02:42:42 -07:00
Jeffrey Pfau 2fc5474d91 Implement addressing mode 1 ROR immediate 2013-04-27 01:54:57 -07:00
Jeffrey Pfau 13c95a2aae Build fixes for linux 2013-04-26 03:08:59 -07:00
Jeffrey Pfau d2e84f0a30 Implement IntrWait 2013-04-26 02:00:59 -07:00
Jeffrey Pfau 301c07dda3 Implement ADC, SBC 2013-04-26 01:25:31 -07:00
Jeffrey Pfau 65e0445375 Implement TST 2013-04-25 00:56:43 -07:00
Jeffrey Pfau cfc3ec4f3b Implement ROR 2013-04-25 00:53:24 -07:00
Jeffrey Pfau 21490dcf51 Implement CMN 2013-04-25 00:48:35 -07:00
Jeffrey Pfau 190f9b41e6 Implement STRB(2) 2013-04-23 02:13:59 -07:00
Jeffrey Pfau 67d25794e1 Fix LDMIA/STMIA 2013-04-20 18:03:59 -07:00
Jeffrey Pfau 14100f19d1 Implement LSL(2) 2013-04-20 18:03:48 -07:00
Jeffrey Pfau cb48145ea3 Move main emulation into thread 2013-04-20 15:54:09 -07:00
Jeffrey Pfau 18fae08450 Fix Load/store shifters 2013-04-20 14:21:42 -07:00
Jeffrey Pfau cd0f75c83f Implement MLA 2013-04-20 13:36:42 -07:00
Jeffrey Pfau bf54a68b0e Implement UMULL 2013-04-20 13:22:10 -07:00
Jeffrey Pfau e272481ccd Implement LDR(2) 2013-04-20 02:57:20 -07:00
Jeffrey Pfau adfd8f6872 Make sure if we reset the CPSR to the SPSR that we check if we get tossed into Thumb 2013-04-19 21:26:00 -07:00
Jeffrey Pfau 633a87269a Initialize cpu->privilegeMode 2013-04-19 21:09:00 -07:00
Jeffrey Pfau 5f1f6088bd Implement MUL 2013-04-18 01:35:48 -07:00
Jeffrey Pfau 783b2a3e09 Implement ADD(5) 2013-04-18 01:24:46 -07:00
Jeffrey Pfau 0048de2108 Fix addressing mode 3 immediate 2013-04-18 01:06:19 -07:00
Jeffrey Pfau 4f8c288f20 Ensure cpsr.t reads back out properly 2013-04-18 00:19:41 -07:00
Jeffrey Pfau ed48ab1c64 Fix storing SPSR 2013-04-18 00:15:45 -07:00
Jeffrey Pfau 062e09ccf5 Implement MSRI 2013-04-18 00:09:28 -07:00
Jeffrey Pfau fdf36f5820 Implement MRS 2013-04-18 00:06:48 -07:00
Jeffrey Pfau b3832205fc Fix some MRS/MSR encoding problems 2013-04-18 00:03:39 -07:00
Jeffrey Pfau 6608ae282c Ensure loads to PC work 2013-04-17 23:54:31 -07:00
Jeffrey Pfau cb03781a5b Implement LDM, STM 2013-04-17 23:44:35 -07:00
Jeffrey Pfau 38b1c8d235 Make sure CPSR is updated for IRQ mode properly 2013-04-17 00:29:20 -07:00
Jeffrey Pfau f30b367c7e Make sure to rewrite active region data when jumping to IRQ handler 2013-04-17 00:24:00 -07:00
Jeffrey Pfau c143dec77d Fix ADD(4) and MOV(3) 2013-04-16 23:52:30 -07:00
Jeffrey Pfau 4b4914afb6 Implement MUL 2013-04-16 23:26:49 -07:00
Jeffrey Pfau 6b07dd33af Implement ASR(1) 2013-04-16 23:24:19 -07:00
Jeffrey Pfau bc9d0690bb Clean up extra backslashes 2013-04-16 19:29:00 -07:00
Jeffrey Pfau 2d0c3bf275 Implement IRQs 2013-04-16 07:50:34 -07:00
Jeffrey Pfau 2fe2c80ae5 Add dummy renderer + frame counting infrastructure from GBA.js 2013-04-15 23:01:40 -07:00
Jeffrey Pfau 9b5d5d6478 Start implementing events + add video stubs 2013-04-15 22:18:28 -07:00
Jeffrey Pfau ecc4775c31 Start implementing instruction timing 2013-04-14 23:12:03 -07:00
Jeffrey Pfau 1ca6487151 Create subdirs 2013-04-14 13:04:24 -07:00