mirror of https://github.com/mgba-emu/mgba.git
Jeffrey Pfau
parent
e5245b6cbb
commit
fde6515a56
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@ -17,92 +17,6 @@ static void _RegisterRamReset(struct GBA* gba) {
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GBALog(gba, GBA_LOG_STUB, "RegisterRamReset unimplemented");
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}
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static void _CpuSet(struct GBA* gba) {
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struct ARMCore* cpu = gba->cpu;
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uint32_t source = cpu->gprs[0];
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uint32_t dest = cpu->gprs[1];
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uint32_t mode = cpu->gprs[2];
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int count = mode & 0x000FFFFF;
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int fill = mode & 0x01000000;
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int wordsize = (mode & 0x04000000) ? 4 : 2;
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int i;
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if (fill) {
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if (wordsize == 4) {
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source &= 0xFFFFFFFC;
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dest &= 0xFFFFFFFC;
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int32_t word = cpu->memory.load32(cpu, source, &cpu->cycles);
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for (i = 0; i < count; ++i) {
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cpu->memory.store32(cpu, dest + (i << 2), word, &cpu->cycles);
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cpu->irqh.processEvents(cpu);
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}
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} else {
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source &= 0xFFFFFFFE;
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dest &= 0xFFFFFFFE;
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uint16_t word = cpu->memory.load16(cpu, source, &cpu->cycles);
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for (i = 0; i < count; ++i) {
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cpu->memory.store16(cpu, dest + (i << 1), word, &cpu->cycles);
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cpu->irqh.processEvents(cpu);
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}
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}
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} else {
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if (wordsize == 4) {
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source &= 0xFFFFFFFC;
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dest &= 0xFFFFFFFC;
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for (i = 0; i < count; ++i) {
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int32_t word = cpu->memory.load32(cpu, source + (i << 2), &cpu->cycles);
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cpu->memory.store32(cpu, dest + (i << 2), word, &cpu->cycles);
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cpu->irqh.processEvents(cpu);
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}
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} else {
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source &= 0xFFFFFFFE;
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dest &= 0xFFFFFFFE;
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for (i = 0; i < count; ++i) {
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uint16_t word = cpu->memory.load16(cpu, source + (i << 1), &cpu->cycles);
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cpu->memory.store16(cpu, dest + (i << 1), word, &cpu->cycles);
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cpu->irqh.processEvents(cpu);
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}
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}
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}
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}
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static void _FastCpuSet(struct GBA* gba) {
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struct ARMCore* cpu = gba->cpu;
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uint32_t source = cpu->gprs[0] & 0xFFFFFFFC;
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uint32_t dest = cpu->gprs[1] & 0xFFFFFFFC;
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uint32_t mode = cpu->gprs[2];
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int count = mode & 0x000FFFFF;
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int storeCycles = cpu->memory.waitMultiple(cpu, dest, 4);
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count = ((count + 7) >> 3) << 3;
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int i;
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if (mode & 0x01000000) {
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int32_t word = cpu->memory.load32(cpu, source, &cpu->cycles);
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for (i = 0; i < count; i += 4) {
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cpu->memory.store32(cpu, dest + ((i + 0) << 2), word, 0);
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cpu->memory.store32(cpu, dest + ((i + 1) << 2), word, 0);
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cpu->memory.store32(cpu, dest + ((i + 2) << 2), word, 0);
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cpu->memory.store32(cpu, dest + ((i + 3) << 2), word, 0);
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cpu->cycles += storeCycles;
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cpu->irqh.processEvents(cpu);
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}
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} else {
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int loadCycles = cpu->memory.waitMultiple(cpu, source, 4);
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for (i = 0; i < count; i += 4) {
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int32_t word0 = cpu->memory.load32(cpu, source + ((i + 0) << 2), 0);
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int32_t word1 = cpu->memory.load32(cpu, source + ((i + 1) << 2), 0);
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int32_t word2 = cpu->memory.load32(cpu, source + ((i + 2) << 2), 0);
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int32_t word3 = cpu->memory.load32(cpu, source + ((i + 3) << 2), 0);
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cpu->cycles += loadCycles;
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cpu->irqh.processEvents(cpu);
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cpu->memory.store32(cpu, dest + ((i + 0) << 2), word0, 0);
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cpu->memory.store32(cpu, dest + ((i + 1) << 2), word1, 0);
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cpu->memory.store32(cpu, dest + ((i + 2) << 2), word2, 0);
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cpu->memory.store32(cpu, dest + ((i + 3) << 2), word3, 0);
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cpu->cycles += storeCycles;
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cpu->irqh.processEvents(cpu);
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}
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}
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}
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static void _BgAffineSet(struct GBA* gba) {
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struct ARMCore* cpu = gba->cpu;
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int i = cpu->gprs[2];
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@ -237,10 +151,8 @@ void GBASwi16(struct ARMCore* cpu, int immediate) {
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cpu->gprs[0] = atan2f(cpu->gprs[1] / 16384.f, cpu->gprs[0] / 16384.f) / (2 * M_PI) * 0x10000;
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break;
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case 0xB:
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_CpuSet(gba);
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break;
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case 0xC:
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_FastCpuSet(gba);
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ARMRaiseSWI(cpu);
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break;
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case 0xD:
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cpu->gprs[0] = GBAChecksum(gba->memory.bios, SIZE_BIOS);
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@ -2,23 +2,47 @@
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#include "gba-memory.h"
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const size_t hleBiosLength = 196;
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const size_t hleBiosLength = 488;
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const uint8_t hleBios[SIZE_BIOS] = {
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0x06, 0x00, 0x00, 0xea, 0xfe, 0xff, 0xff, 0xea, 0x05, 0x00, 0x00, 0xea,
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0xfe, 0xff, 0xff, 0xea, 0xfe, 0xff, 0xff, 0xea, 0x00, 0x00, 0xa0, 0xe1,
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0x0e, 0x00, 0x00, 0xea, 0xfe, 0xff, 0xff, 0xea, 0x02, 0xf3, 0xa0, 0xe3,
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0x1a, 0x00, 0x00, 0xea, 0xfe, 0xff, 0xff, 0xea, 0x02, 0xf3, 0xa0, 0xe3,
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0x00, 0x00, 0x5d, 0xe3, 0x01, 0xd3, 0xa0, 0x03, 0x20, 0xd0, 0x4d, 0x02,
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0x04, 0x40, 0x2d, 0xe9, 0x02, 0x20, 0x5e, 0xe5, 0x04, 0x00, 0x52, 0xe3,
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0x0b, 0x00, 0x00, 0x0b, 0x05, 0x00, 0x52, 0xe3, 0x01, 0x00, 0xa0, 0x03,
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0x01, 0x10, 0xa0, 0x03, 0x07, 0x00, 0x00, 0x0b, 0x04, 0x40, 0xbd, 0xe8,
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0x0e, 0xf0, 0xb0, 0xe1, 0x0f, 0x50, 0x2d, 0xe9, 0x01, 0x03, 0xa0, 0xe3,
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0x30, 0x40, 0x2d, 0xe9, 0x02, 0x40, 0x5e, 0xe5, 0x54, 0x50, 0xa0, 0xe3,
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0x04, 0x41, 0x95, 0xe7, 0x00, 0x00, 0x54, 0xe3, 0x0f, 0xe0, 0xa0, 0xe1,
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0x14, 0xff, 0x2f, 0x11, 0x30, 0x40, 0xbd, 0xe8, 0x0e, 0xf0, 0xb0, 0xe1,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x00, 0x00,
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0x7c, 0x01, 0x00, 0x00, 0x0f, 0x50, 0x2d, 0xe9, 0x01, 0x03, 0xa0, 0xe3,
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0x00, 0xe0, 0x8f, 0xe2, 0x04, 0xf0, 0x10, 0xe5, 0x0f, 0x50, 0xbd, 0xe8,
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0x04, 0xf0, 0x5e, 0xe2, 0x10, 0x40, 0x2d, 0xe9, 0x00, 0x30, 0x0f, 0xe1,
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0x80, 0x30, 0xc3, 0xe3, 0x03, 0xf0, 0x29, 0xe1, 0x01, 0x43, 0xa0, 0xe3,
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0x00, 0x00, 0x50, 0xe3, 0x00, 0x00, 0xa0, 0xe3, 0x01, 0x20, 0xa0, 0xe3,
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0x00, 0x00, 0x00, 0x0a, 0x01, 0x03, 0xc4, 0xe5, 0x04, 0x22, 0xc4, 0xe5,
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0xb8, 0x30, 0x54, 0xe1, 0x01, 0x30, 0x13, 0xe0, 0x01, 0x30, 0x23, 0x10,
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0xb8, 0x30, 0x44, 0x11, 0x04, 0x02, 0xc4, 0xe5, 0xf7, 0xff, 0xff, 0x0a,
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0x00, 0x00, 0x0f, 0xe1, 0x80, 0x00, 0x80, 0xe3, 0x00, 0xf0, 0x29, 0xe1,
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0x10, 0x80, 0xbd, 0xe8
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0x04, 0xf0, 0x5e, 0xe2, 0x01, 0x00, 0xa0, 0xe3, 0x01, 0x10, 0xa0, 0xe3,
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0x00, 0x40, 0x2d, 0xe9, 0x00, 0x50, 0x4f, 0xe1, 0x1f, 0xf0, 0x29, 0xe3,
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0x01, 0x43, 0xa0, 0xe3, 0x00, 0x00, 0x50, 0xe3, 0x00, 0x00, 0xa0, 0xe3,
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0x01, 0x20, 0xa0, 0xe3, 0x00, 0x00, 0x00, 0x0a, 0x01, 0x03, 0xc4, 0xe5,
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0x08, 0x02, 0xc4, 0xe5, 0xb8, 0x30, 0x54, 0xe1, 0x01, 0x30, 0x13, 0xe0,
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0x01, 0x30, 0x23, 0x10, 0xb8, 0x30, 0x44, 0x11, 0x08, 0x22, 0xc4, 0xe5,
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0xf7, 0xff, 0xff, 0x0a, 0x93, 0xf0, 0x29, 0xe3, 0x05, 0xf0, 0x69, 0xe1,
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0x00, 0x80, 0xbd, 0xe8, 0x9f, 0xf0, 0x29, 0xe3, 0x02, 0x36, 0xa0, 0xe1,
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0x23, 0x36, 0xa0, 0xe1, 0x01, 0x04, 0x12, 0xe3, 0x0d, 0x00, 0x00, 0x0a,
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0x01, 0x03, 0x12, 0xe3, 0x04, 0x00, 0x00, 0x0a, 0x04, 0x00, 0xb0, 0xe8,
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0x04, 0x00, 0xa1, 0xe8, 0x01, 0x30, 0x53, 0xe2, 0xfc, 0xff, 0xff, 0x1a,
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0x13, 0x00, 0x00, 0xea, 0x01, 0x00, 0xc0, 0xe3, 0x01, 0x10, 0xc1, 0xe3,
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0xb0, 0x20, 0xd0, 0xe1, 0xb2, 0x20, 0xc1, 0xe0, 0x01, 0x30, 0x53, 0xe2,
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0xfc, 0xff, 0xff, 0x1a, 0x0c, 0x00, 0x00, 0xea, 0x01, 0x03, 0x12, 0xe3,
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0x04, 0x00, 0x00, 0x0a, 0x04, 0x00, 0xb0, 0xe8, 0x04, 0x00, 0xa1, 0xe8,
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0x01, 0x30, 0x53, 0xe2, 0xfb, 0xff, 0xff, 0x1a, 0x05, 0x00, 0x00, 0xea,
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0x01, 0x00, 0xc0, 0xe3, 0x01, 0x10, 0xc1, 0xe3, 0xb2, 0x20, 0xd0, 0xe0,
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0xb2, 0x20, 0xc1, 0xe0, 0x01, 0x30, 0x53, 0xe2, 0xfb, 0xff, 0xff, 0x1a,
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0x93, 0xf0, 0x29, 0xe3, 0x1e, 0xff, 0x2f, 0xe1, 0x9f, 0xf0, 0x29, 0xe3,
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0xf0, 0x07, 0x2d, 0xe9, 0x02, 0x36, 0xa0, 0xe1, 0x23, 0x36, 0xa0, 0xe1,
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0x01, 0x04, 0x12, 0xe3, 0x0c, 0x00, 0x00, 0x0a, 0x10, 0x00, 0xb0, 0xe8,
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0x03, 0x20, 0xa0, 0xe1, 0x04, 0x50, 0xa0, 0xe1, 0x04, 0x30, 0xa0, 0xe1,
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0x04, 0x60, 0xa0, 0xe1, 0x04, 0x70, 0xa0, 0xe1, 0x04, 0x80, 0xa0, 0xe1,
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0x04, 0x90, 0xa0, 0xe1, 0x04, 0xa0, 0xa0, 0xe1, 0xf8, 0x07, 0xa1, 0xe8,
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0x08, 0x20, 0x52, 0xe2, 0xfc, 0xff, 0xff, 0xca, 0x04, 0x00, 0x00, 0xea,
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0x03, 0x20, 0xa0, 0xe1, 0xf8, 0x07, 0xb0, 0xe8, 0xf8, 0x07, 0xa1, 0xe8,
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0x08, 0x20, 0x52, 0xe2, 0xfb, 0xff, 0xff, 0xca, 0xf0, 0x07, 0xbd, 0xe8,
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0x93, 0xf0, 0x29, 0xe3, 0x1e, 0xff, 0x2f, 0xe1
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};
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@ -18,17 +18,32 @@ swiBase:
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cmp sp, #0
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moveq sp, #0x04000000
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subeq sp, #0x20
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stmfd sp!, {r2, lr}
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ldrb r2, [lr, #-2]
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cmp r2, #4
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bleq IntrWait
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cmp r2, #5
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moveq r0, #1
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moveq r1, #1
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bleq IntrWait
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ldmfd sp!, {r2, lr}
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stmfd sp!, {r4-r5, lr}
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ldrb r4, [lr, #-2]
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mov r5, #swiTable
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ldr r4, [r5, r4, lsl #2]
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cmp r4, #0
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mov lr, pc
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bxne r4
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ldmfd sp!, {r4-r5, lr}
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movs pc, lr
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swiTable:
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.word SoftReset
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.word RegisterRamReset
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.word Halt
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.word Stop
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.word IntrWait
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.word VBlankIntrWait
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.word Div
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.word DivArm
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.word Sqrt
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.word ArcTan
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.word ArcTan2
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.word CpuSet
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.word CpuFastSet
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# ... The rest of this table isn't needed if the rest aren't implemented
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irqBase:
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stmfd sp!, {r0-r3, r12, lr}
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mov r0, #0x04000000
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@ -37,33 +52,117 @@ ldr pc, [r0, #-4]
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ldmfd sp!, {r0-r3, r12, lr}
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subs pc, lr, #4
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VBlankIntrWait:
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mov r0, #1
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mov r1, #1
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IntrWait:
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stmfd sp!, {r4, lr}
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# Save inputs
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mrs r3, cpsr
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bic r3, #0x80
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msr cpsr, r3
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stmfd sp!, {lr}
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mrs r5, spsr
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msr cpsr, #0x1F
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# Pull current interrupts enabled and add the ones we need
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mov r4, #0x04000000
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# See if we want to return immediately
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cmp r0, #0
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mov r0, #0
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mov r2, #1
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beq .L1
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beq 1f
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# Halt
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.L0:
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0:
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strb r0, [r4, #0x301]
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.L1:
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1:
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# Check which interrupts were acknowledged
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strb r2, [r4, #0x204]
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strb r0, [r4, #0x208]
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ldrh r3, [r4, #-8]
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ands r3, r1
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eorne r3, r1
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strneh r3, [r4, #-8]
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strb r0, [r4, #0x204]
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beq .L0
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#Restore state
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mrs r0, cpsr
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orr r0, #0x80
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msr cpsr, r0
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ldmfd sp!, {r4, pc}
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strb r2, [r4, #0x208]
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beq 0b
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msr cpsr, #0x93
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msr spsr, r5
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ldmfd sp!, {pc}
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CpuSet:
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msr cpsr, #0x9F
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mov r3, r2, lsl #12
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mov r3, r3, lsr #12
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tst r2, #0x01000000
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beq 0f
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# Fill
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tst r2, #0x04000000
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beq 1f
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# Word
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ldmia r0!, {r2}
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2:
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stmia r1!, {r2}
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subs r3, #1
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bne 2b
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b 3f
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# Halfword
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1:
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bic r0, #1
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bic r1, #1
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ldrh r2, [r0]
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2:
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strh r2, [r1], #2
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subs r3, #1
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bne 2b
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b 3f
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# Copy
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0:
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tst r2, #0x04000000
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beq 1f
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# Word
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2:
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ldmia r0!, {r2}
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stmia r1!, {r2}
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subs r3, #1
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bne 2b
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b 3f
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# Halfword
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1:
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bic r0, #1
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bic r1, #1
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2:
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ldrh r2, [r0], #2
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strh r2, [r1], #2
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subs r3, #1
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bne 2b
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3:
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msr cpsr, #0x93
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bx lr
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CpuFastSet:
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msr cpsr, #0x9F
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stmfd sp!, {r4-r10}
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mov r3, r2, lsl #12
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mov r3, r3, lsr #12
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tst r2, #0x01000000
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beq 0f
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# Fill
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ldmia r0!, {r4}
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mov r2, r3
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mov r5, r4
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mov r3, r4
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mov r6, r4
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mov r7, r4
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mov r8, r4
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mov r9, r4
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mov r10, r4
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1:
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stmia r1!, {r3-r10}
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subs r2, #8
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bgt 1b
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b 2f
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# Copy
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0:
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mov r2, r3
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1:
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ldmia r0!, {r3-r10}
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||||
stmia r1!, {r3-r10}
|
||||
subs r2, #8
|
||||
bgt 1b
|
||||
2:
|
||||
ldmfd sp!, {r4-r10}
|
||||
msr cpsr, #0x93
|
||||
bx lr
|
||||
|
|
|
|||
Loading…
Reference in New Issue