mirror of https://github.com/mgba-emu/mgba.git
Implement ADD, ADC, RSB, RSC, SUB
This commit is contained in:
Jeffrey Pfau
parent
c1a8042db4
commit
fd4ee12eb5
162
src/arm.c
162
src/arm.c
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@ -81,7 +81,10 @@ inline void ARMCycle(struct ARMCore* cpu) {
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// Instruction definitions
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// Beware pre-processor antics
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#define ARM_CARRY_FROM ((((M) | (N)) >> 31) && !((D) >> 31)))
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#define ARM_CARRY_FROM(M, N, D) ((((M) | (N)) >> 31) && !((D) >> 31))
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#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
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#define ARM_V_ADDITION(M, N, D) (!(((M) ^ (N)) >> 31) && (((M) ^ (D)) >> 31) && (((N) ^ (D)) >> 31))
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#define ARM_V_SUBTRACTION(M, N, D) ((((M) ^ (N)) >> 31) && (((M) ^ (D)) >> 31))
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#define ARM_COND_EQ (cpu->cpsr.z)
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#define ARM_COND_NE (!cpu->cpsr.z)
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@ -107,7 +110,19 @@ inline void ARMCycle(struct ARMCore* cpu) {
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cpu->cpsr.n = (D) >> 31; \
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cpu->cpsr.z = !(D); \
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cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
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} \
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cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
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}
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#define ARM_SUBTRACTION_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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cpu->cpsr.n = (D) >> 31; \
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cpu->cpsr.z = !(D); \
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cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
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cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
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}
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#define ARM_NEUTRAL_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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@ -117,10 +132,10 @@ inline void ARMCycle(struct ARMCore* cpu) {
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cpu->cpsr.n = (D) >> 31; \
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cpu->cpsr.z = !(D); \
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cpu->cpsr.c = cpu->shifterCarryOut; \
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} \
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}
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// TODO: shifter
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#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, S, S_BODY, BODY) \
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#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, S, S_BODY, BODY, POST_BODY) \
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static void _ARMInstruction ## NAME ## S ## COND (struct ARMCore* cpu, uint32_t opcode) { \
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if (!COND_BODY) { \
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return; \
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@ -129,47 +144,71 @@ inline void ARMCycle(struct ARMCore* cpu) {
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int rn = (opcode >> 16) & 0xF; \
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BODY; \
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S_BODY; \
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POST_BODY; \
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}
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#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, , , BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, S, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, S, S_BODY, BODY)
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#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, S, S_BODY, BODY, POST_BODY)
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// Begin ALU definitions
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DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
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int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
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cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand; \
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)
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cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand; \
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)
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cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
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int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
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DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
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int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
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int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
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DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
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int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
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int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
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DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
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int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
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// End ALU definitions
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#define DECLARE_INSTRUCTION_ARM(COND, NAME) \
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_ARMInstruction ## NAME ## COND
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@ -187,18 +226,7 @@ DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand
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DIRECTIVE \
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// TODO: MUL
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#define DECLARE_ARM_ALU_EX_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
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DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DECLARE_INSTRUCTION_ARM(COND, ALU), \
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0, \
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DECLARE_INSTRUCTION_ARM(COND, ALU), \
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0, \
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DECLARE_INSTRUCTION_ARM(COND, ALU), \
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0, \
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DECLARE_INSTRUCTION_ARM(COND, ALU), \
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0
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#define DECLARE_ARM_ALU_BLOCK(COND, ALU) \
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#define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
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DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
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DECLARE_INSTRUCTION_ARM(COND, ALU), \
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0, \
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@ -210,22 +238,22 @@ DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand
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0
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#define DECLARE_COND_BLOCK(COND) \
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DECLARE_ARM_ALU_EX_BLOCK(COND, AND, MUL, STRH, 0, 0), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, EOR, MLA, STRH, 0, 0), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, EORS, MLAS, LDRH, LDRSB, LDRSH)/*, \
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DECLARE_ARM_ALU_EX_BLOCK(COND, SUB, 0, STRH, 0, 0), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, SUBS, 0, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, RSB, 0, STRH, 0, 0), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, RSBS, 0, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, ADD, UMULL, STRH, 0, 0), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, ADDS, UMULLS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, ADC, UMLAL, STRH, 0, 0), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, ADCS, UMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, SBC, SMULL, STRH, 0, 0), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, SBCS, SMULLS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, RSC, SMLAL, STRH, 0, 0), \
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DECLARE_ARM_ALU_EX_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH)*/
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DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, SUB, 0, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, SUBS, 0, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, RSB, 0, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, RSBS, 0, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH)
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static const ARMInstruction armTable[0xF000] = {
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DECLARE_COND_BLOCK(EQ),
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