mirror of https://github.com/mgba-emu/mgba.git
Some instructions can write to pc directly
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parent
01d4672f56
commit
fc132b4d93
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@ -139,6 +139,7 @@ DEFINE_DATA_FORM_5_DECODER_THUMB(MVN, MVN, ARM_OPERAND_AFFECTED_1)
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info->op1.reg = (opcode & 0x0007) | H1; \
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info->op1.reg = (opcode & 0x0007) | H1; \
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info->op2.reg = ((opcode >> 3) & 0x0007) | H2; \
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info->op2.reg = ((opcode >> 3) & 0x0007) | H2; \
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info->accessesSpecialRegisters = info->op1.reg > 12 || info->op2.reg > 12; \
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info->accessesSpecialRegisters = info->op1.reg > 12 || info->op2.reg > 12; \
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info->branches = info->op1.reg == ARM_PC; \
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info->affectsCPSR = CPSR; \
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info->affectsCPSR = CPSR; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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AFFECTED | \
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AFFECTED | \
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@ -224,6 +225,7 @@ DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STRH, STORE_CYCLES)
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info->memory.baseReg = RN; \
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info->memory.baseReg = RN; \
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info->accessesSpecialRegisters = SPECIAL_REG; \
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info->accessesSpecialRegisters = SPECIAL_REG; \
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info->op1.immediate = (opcode & 0xFF) | ADDITIONAL_REG; \
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info->op1.immediate = (opcode & 0xFF) | ADDITIONAL_REG; \
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info->branches = info->op1.immediate & (1 << ARM_PC); \
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info->operandFormat = ARM_OPERAND_MEMORY_1; \
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info->operandFormat = ARM_OPERAND_MEMORY_1; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_POST_INCREMENT;)
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ARM_MEMORY_POST_INCREMENT;)
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