mirror of https://github.com/mgba-emu/mgba.git
Implement LDR(1)
This commit is contained in:
parent
33fc9587cc
commit
f86fb9dc74
|
@ -101,7 +101,7 @@ DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
|
||||||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, ARM_STUB)
|
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, ARM_STUB)
|
||||||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
|
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
|
||||||
|
|
||||||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, ARM_STUB)
|
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
|
||||||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
|
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
|
||||||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
|
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
|
||||||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
|
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
|
||||||
|
|
Loading…
Reference in New Issue