From f6cb2c4a0a4f8c29837b66a34f8090ed25f2560f Mon Sep 17 00:00:00 2001
From: Vicki Pfau <vi@endrift.com>
Date: Fri, 26 Jun 2020 01:17:19 -0700
Subject: [PATCH] ARM: Fix LDM^ writeback to user-mode register

---
 CHANGES           | 1 +
 src/arm/isa-arm.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/CHANGES b/CHANGES
index ce5315c4a..a79b7e069 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,5 +1,6 @@
 0.8.3: (Future)
 Emulation fixes:
+ - ARM: Fix LDM^ writeback to user-mode register
  - GB Memory: Fix OAM DMA from top 8 kB
  - GB MBC: Fix MBC1 RAM enable bit selection
  - GB MBC: Fix MBC2 bit selection
diff --git a/src/arm/isa-arm.c b/src/arm/isa-arm.c
index c88345f90..a0e79313c 100644
--- a/src/arm/isa-arm.c
+++ b/src/arm/isa-arm.c
@@ -439,9 +439,9 @@ ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
 		uint32_t address = cpu->gprs[rn]; \
 		S_PRE; \
 		address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, &currentCycles); \
+		WRITEBACK; \
 		S_POST; \
-		POST_BODY; \
-		WRITEBACK;)
+		POST_BODY;)
 
 
 #define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \