diff --git a/src/arm.c b/src/arm.c
index 56577be74..1968db8ef 100644
--- a/src/arm.c
+++ b/src/arm.c
@@ -375,6 +375,14 @@ DEFINE_INSTRUCTION_ARM(SWPB,)
 
 // End load/store definitions
 
+// Begin branch definitions
+
+DEFINE_INSTRUCTION_ARM(B,)
+DEFINE_INSTRUCTION_ARM(BL,)
+DEFINE_INSTRUCTION_ARM(BX,)
+
+// End branch definitions
+
 // TODO
 DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
 DEFINE_INSTRUCTION_ARM(MSR,)
@@ -436,6 +444,12 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
 	DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W)), \
 	DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W))
 
+#define DECLARE_ARM_BRANCH_BLOCK(COND, NAME) \
+	DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \
+	DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \
+	DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \
+	DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME)))
+
 #define LDRHW ILL
 #define LDRSBW ILL
 #define LDRSHW ILL
@@ -472,7 +486,22 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
 	DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRHIUW, LDRSBIUW, LDRSHIUW), \
 	DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
-	DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHPW, ILL, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, MSR), \
+	DECLARE_INSTRUCTION_ARM(COND, BX), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, STRHPW), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
 	DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRHIP, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
@@ -613,9 +642,9 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
 	DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, ), \
 	DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, ), \
 	DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, W), \
-	DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, W)//, \
-	// DECLARE_ARM_BRANCH_BLOCK(COND, B), \
-	// DECLARE_ARM_BRANCH_BLOCK(COND, BL), \
+	DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, W), \
+	DECLARE_ARM_BRANCH_BLOCK(COND, B), \
+	DECLARE_ARM_BRANCH_BLOCK(COND, BL)//, \
 	// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \
 	// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \
 	// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \