mirror of https://github.com/mgba-emu/mgba.git
LR35902: Simplify pipeline
This commit is contained in:
Jeffrey Pfau
parent
0bfbc2079e
commit
e96da4c7b9
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@ -80,7 +80,7 @@ DEFINE_INSTRUCTION_LR35902(CALLUpdateSPL,
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DEFINE_INSTRUCTION_LR35902(CALLUpdateSPH,
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cpu->index = cpu->sp + 1;
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cpu->bus = (cpu->pc + 2) >> 8;
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE;
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cpu->executionState = LR35902_CORE_MEMORY_STORE;
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cpu->instruction = _LR35902InstructionCALLUpdateSPL;)
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#define DEFINE_CALL_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
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@ -90,7 +90,7 @@ DEFINE_INSTRUCTION_LR35902(CALLUpdateSPH,
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cpu->sp -= 2; \
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cpu->index = cpu->sp; \
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cpu->bus = cpu->pc + 2; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionCALLUpdateSPH; \
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} else { \
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cpu->executionState = LR35902_CORE_READ_PC; \
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@ -110,7 +110,7 @@ DEFINE_INSTRUCTION_LR35902(RETUpdateSPH,
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if (cpu->condition) {
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cpu->index = cpu->sp + 1;
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cpu->pc = cpu->bus;
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_LOAD;
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cpu->executionState = LR35902_CORE_MEMORY_LOAD;
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cpu->instruction = _LR35902InstructionRETUpdateSPL;
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})
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@ -118,7 +118,7 @@ DEFINE_INSTRUCTION_LR35902(RETUpdateSPH,
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DEFINE_INSTRUCTION_LR35902(RET ## CONDITION_NAME, \
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cpu->condition = CONDITION; \
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cpu->index = cpu->sp; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_LOAD; \
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cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
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cpu->instruction = _LR35902InstructionRETUpdateSPH;)
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DEFINE_CONDITIONAL_INSTRUCTION_LR35902(RET)
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@ -182,7 +182,7 @@ DEFINE_CONDITIONAL_INSTRUCTION_LR35902(RET)
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#define DEFINE_LDHL__INSTRUCTION_LR35902(NAME, OPERAND) \
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DEFINE_INSTRUCTION_LR35902(LDHL_ ## NAME, \
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cpu->bus = OPERAND; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionLDHL_Bus;)
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#define DEFINE_LDA__INSTRUCTION_LR35902(NAME, OPERAND) \
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@ -200,7 +200,7 @@ DEFINE_CONDITIONAL_INSTRUCTION_LR35902(RET)
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DEFINE_INSTRUCTION_LR35902(LDHL_Bus, \
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cpu->index = LR35902ReadHL(cpu); \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionNOP;)
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DEFINE_INSTRUCTION_LR35902(LDHL_, \
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@ -210,7 +210,7 @@ DEFINE_INSTRUCTION_LR35902(LDHL_, \
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#define DEFINE_ALU_INSTRUCTION_LR35902(NAME) \
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DEFINE_ ## NAME ## _INSTRUCTION_LR35902(Bus, cpu->bus); \
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DEFINE_INSTRUCTION_LR35902(NAME ## HL, \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_LOAD; \
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cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
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cpu->index = LR35902ReadHL(cpu); \
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cpu->instruction = _LR35902Instruction ## NAME ## Bus;) \
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DEFINE_INSTRUCTION_LR35902(NAME, \
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@ -253,7 +253,7 @@ DEFINE_INSTRUCTION_LR35902(LDBC, \
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DEFINE_INSTRUCTION_LR35902(LDBC_A, \
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cpu->index = LR35902ReadBC(cpu); \
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cpu->bus = cpu->a; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionNOP;)
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DEFINE_INSTRUCTION_LR35902(LDDEDelay, \
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@ -268,7 +268,7 @@ DEFINE_INSTRUCTION_LR35902(LDDE, \
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DEFINE_INSTRUCTION_LR35902(LDDE_A, \
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cpu->index = LR35902ReadDE(cpu); \
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cpu->bus = cpu->a; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionNOP;)
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DEFINE_INSTRUCTION_LR35902(LDHLDelay, \
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@ -295,20 +295,20 @@ DEFINE_INSTRUCTION_LR35902(LDIHLA, \
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cpu->index = LR35902ReadHL(cpu); \
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LR35902WriteHL(cpu, cpu->index + 1); \
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cpu->bus = cpu->a; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionNOP;)
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DEFINE_INSTRUCTION_LR35902(LDDHLA, \
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cpu->index = LR35902ReadHL(cpu); \
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LR35902WriteHL(cpu, cpu->index - 1); \
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cpu->bus = cpu->a; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionNOP;)
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DEFINE_INSTRUCTION_LR35902(LDIAFinish, \
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cpu->index |= cpu->bus << 8;
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cpu->bus = cpu->a; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionNOP;)
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DEFINE_INSTRUCTION_LR35902(LDIADelay, \
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@ -322,7 +322,7 @@ DEFINE_INSTRUCTION_LR35902(LDIA, \
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DEFINE_INSTRUCTION_LR35902(LDAIFinish, \
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cpu->index |= cpu->bus << 8;
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_LOAD; \
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cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
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cpu->instruction = _LR35902InstructionLDA_Bus;)
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DEFINE_INSTRUCTION_LR35902(LDAIDelay, \
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@ -336,18 +336,18 @@ DEFINE_INSTRUCTION_LR35902(LDAI, \
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DEFINE_INSTRUCTION_LR35902(LDAIOC, \
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cpu->index = 0xFF00 | cpu->c; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_LOAD; \
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cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
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cpu->instruction = _LR35902InstructionLDA_Bus;)
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DEFINE_INSTRUCTION_LR35902(LDIOCA, \
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cpu->index = 0xFF00 | cpu->c; \
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cpu->bus = cpu->a; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionNOP;)
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DEFINE_INSTRUCTION_LR35902(LDAIODelay, \
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cpu->index = 0xFF00 | cpu->bus; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_LOAD; \
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cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
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cpu->instruction = _LR35902InstructionLDA_Bus;)
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DEFINE_INSTRUCTION_LR35902(LDAIO, \
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@ -357,7 +357,7 @@ DEFINE_INSTRUCTION_LR35902(LDAIO, \
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DEFINE_INSTRUCTION_LR35902(LDIOADelay, \
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cpu->index = 0xFF00 | cpu->bus; \
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cpu->bus = cpu->a; \
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cpu->executionState = LR35902_CORE_MEMORY_MOVE_INDEX_STORE; \
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cpu->executionState = LR35902_CORE_MEMORY_STORE; \
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cpu->instruction = _LR35902InstructionNOP;)
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DEFINE_INSTRUCTION_LR35902(LDIOA, \
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@ -88,8 +88,6 @@ void LR35902Tick(struct LR35902Core* cpu) {
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// TODO: stall
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}
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cpu->bus = cpu->memory.load8(cpu, cpu->pc);
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break;
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case LR35902_CORE_DECODE:
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cpu->instruction = _lr35902InstructionTable[cpu->bus];
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++cpu->pc;
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break;
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@ -105,16 +103,8 @@ void LR35902Tick(struct LR35902Core* cpu) {
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case LR35902_CORE_READ_PC:
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cpu->bus = cpu->memory.load8(cpu, cpu->pc);
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++cpu->pc;
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cpu->executionState = LR35902_CORE_READ_PC_STALL;
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break;
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case LR35902_CORE_MEMORY_MOVE_INDEX_LOAD:
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cpu->executionState = LR35902_CORE_MEMORY_LOAD;
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break;
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case LR35902_CORE_MEMORY_MOVE_INDEX_STORE:
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cpu->executionState = LR35902_CORE_MEMORY_STORE;
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break;
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case LR35902_CORE_READ_PC_STALL:
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case LR35902_CORE_STALL:
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default:
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break;
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}
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if (cpu->cycles >= cpu->nextEvent) {
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@ -36,16 +36,13 @@ union FlagRegister {
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enum LR35902ExecutionState {
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LR35902_CORE_FETCH = 0,
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LR35902_CORE_DECODE,
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LR35902_CORE_STALL,
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LR35902_CORE_EXECUTE,
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LR35902_CORE_IDLE_0,
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LR35902_CORE_IDLE_1,
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LR35902_CORE_EXECUTE = 3,
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LR35902_CORE_MEMORY_LOAD = 5,
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LR35902_CORE_MEMORY_STORE = 9,
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LR35902_CORE_MEMORY_MOVE_INDEX_LOAD,
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LR35902_CORE_MEMORY_MOVE_INDEX_STORE,
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LR35902_CORE_READ_PC,
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LR35902_CORE_READ_PC_STALL,
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LR35902_CORE_MEMORY_LOAD = 4,
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LR35902_CORE_MEMORY_STORE = 8,
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LR35902_CORE_READ_PC = 12,
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};
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struct LR35902Memory {
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