From e85e8968f254f74df6c3f6baf1ac60788381aa7b Mon Sep 17 00:00:00 2001
From: Jeffrey Pfau <jeffrey@endrift.com>
Date: Mon, 26 Jan 2015 01:42:21 -0800
Subject: [PATCH] ARM7: Tidy up decoder MSR and MRS instructions

---
 src/arm/decoder-arm.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/arm/decoder-arm.c b/src/arm/decoder-arm.c
index 255a631c8..27f692de2 100644
--- a/src/arm/decoder-arm.c
+++ b/src/arm/decoder-arm.c
@@ -400,7 +400,7 @@ DEFINE_DECODER_ARM(MSRR, MSR,
 		ARM_OPERAND_AFFECTED_1 |
 		ARM_OPERAND_REGISTER_2;)
 
-DEFINE_DECODER_ARM(MRS, MRS, info->affectsCPSR = 1;
+DEFINE_DECODER_ARM(MRS, MRS,
 	info->affectsCPSR = 1;
 	info->op1.reg = (opcode >> 12) & 0xF;
 	info->op2.reg = ARM_CPSR;
@@ -409,8 +409,7 @@ DEFINE_DECODER_ARM(MRS, MRS, info->affectsCPSR = 1;
 		ARM_OPERAND_AFFECTED_1 |
 		ARM_OPERAND_REGISTER_2;)
 
-DEFINE_DECODER_ARM(MRSR, MRS, info->affectsCPSR = 1;
-	info->affectsCPSR = 1;
+DEFINE_DECODER_ARM(MRSR, MRS,
 	info->op1.reg = (opcode >> 12) & 0xF;
 	info->op2.reg = ARM_SPSR;
 	info->op2.psrBits = 0;
@@ -418,7 +417,7 @@ DEFINE_DECODER_ARM(MRSR, MRS, info->affectsCPSR = 1;
 		ARM_OPERAND_AFFECTED_1 |
 		ARM_OPERAND_REGISTER_2;)
 
-DEFINE_DECODER_ARM(MSRI, MSR, info->affectsCPSR = 1;
+DEFINE_DECODER_ARM(MSRI, MSR,
 	int rotate = (opcode & 0x00000F00) >> 7;
 	int32_t operand = ROR(opcode & 0x000000FF, rotate);
 	info->affectsCPSR = 1;
@@ -429,10 +428,9 @@ DEFINE_DECODER_ARM(MSRI, MSR, info->affectsCPSR = 1;
 		ARM_OPERAND_AFFECTED_1 |
 		ARM_OPERAND_IMMEDIATE_2;)
 
-DEFINE_DECODER_ARM(MSRRI, MSR, info->affectsCPSR = 1;
+DEFINE_DECODER_ARM(MSRRI, MSR,
 	int rotate = (opcode & 0x00000F00) >> 7;
 	int32_t operand = ROR(opcode & 0x000000FF, rotate);
-	info->affectsCPSR = 1;
 	info->op1.reg = ARM_SPSR;
 	info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
 	info->op2.immediate = operand;