mirror of https://github.com/mgba-emu/mgba.git
ARM7: Flush prefetch cache when loading CPSR via MSR
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@ -40,6 +40,7 @@ Misc:
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- GBA Video: Null renderer should return proper register values
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- Libretro: Disable logging game errors, BIOS calls and stubs in release builds
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- ARM7: Support forcing Thumb mode via MSR
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- ARM7: Flush prefetch cache when loading CPSR via MSR
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0.4.0: (2016-02-02)
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Features:
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@ -636,7 +636,14 @@ DEFINE_INSTRUCTION_ARM(MSR,
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ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
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}
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_ARMReadCPSR(cpu);)
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_ARMReadCPSR(cpu);
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if (cpu->executionMode == MODE_THUMB) {
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LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
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LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
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} else {
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LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
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LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
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})
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DEFINE_INSTRUCTION_ARM(MSRR,
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int c = opcode & 0x00010000;
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@ -663,11 +670,21 @@ DEFINE_INSTRUCTION_ARM(MSRI,
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if (mask & PSR_USER_MASK) {
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
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}
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if (mask & PSR_STATE_MASK) {
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
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}
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if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
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ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
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}
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_ARMReadCPSR(cpu);)
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_ARMReadCPSR(cpu);
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if (cpu->executionMode == MODE_THUMB) {
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LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
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LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
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} else {
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LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
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LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
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})
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DEFINE_INSTRUCTION_ARM(MSRRI,
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int c = opcode & 0x00010000;
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@ -85,8 +85,6 @@ static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode execution
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break;
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case MODE_THUMB:
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cpu->cpsr.t = 1;
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cpu->prefetch[0] &= 0xFFFF;
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cpu->prefetch[1] &= 0xFFFF;
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}
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cpu->nextEvent = cpu->cycles;
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}
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