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ARM7: Flush prefetch cache when loading CPSR via MSR

This commit is contained in:
Jeffrey Pfau 2016-05-16 01:18:09 -07:00
parent b5ff48a74e
commit e81de71f50
3 changed files with 20 additions and 4 deletions
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1
CHANGES
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@ -40,6 +40,7 @@ Misc:
- GBA Video: Null renderer should return proper register values - GBA Video: Null renderer should return proper register values
- Libretro: Disable logging game errors, BIOS calls and stubs in release builds - Libretro: Disable logging game errors, BIOS calls and stubs in release builds
- ARM7: Support forcing Thumb mode via MSR - ARM7: Support forcing Thumb mode via MSR
- ARM7: Flush prefetch cache when loading CPSR via MSR
0.4.0: (2016-02-02) 0.4.0: (2016-02-02)
Features: Features:

21
src/arm/isa-arm.c
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@ -636,7 +636,14 @@ DEFINE_INSTRUCTION_ARM(MSR,
ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010)); ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK); cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
} }
_ARMReadCPSR(cpu);) _ARMReadCPSR(cpu);
if (cpu->executionMode == MODE_THUMB) {
LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
} else {
LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
})
DEFINE_INSTRUCTION_ARM(MSRR, DEFINE_INSTRUCTION_ARM(MSRR,
int c = opcode & 0x00010000; int c = opcode & 0x00010000;
@ -663,11 +670,21 @@ DEFINE_INSTRUCTION_ARM(MSRI,
if (mask & PSR_USER_MASK) { if (mask & PSR_USER_MASK) {
cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK); cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
} }
if (mask & PSR_STATE_MASK) {
cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
}
if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) { if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010)); ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK); cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
} }
_ARMReadCPSR(cpu);) _ARMReadCPSR(cpu);
if (cpu->executionMode == MODE_THUMB) {
LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
} else {
LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
})
DEFINE_INSTRUCTION_ARM(MSRRI, DEFINE_INSTRUCTION_ARM(MSRRI,
int c = opcode & 0x00010000; int c = opcode & 0x00010000;

2
src/arm/isa-inlines.h
View File

@ -85,8 +85,6 @@ static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode execution
break; break;
case MODE_THUMB: case MODE_THUMB:
cpu->cpsr.t = 1; cpu->cpsr.t = 1;
cpu->prefetch[0] &= 0xFFFF;
cpu->prefetch[1] &= 0xFFFF;
} }
cpu->nextEvent = cpu->cycles; cpu->nextEvent = cpu->cycles;
} }