mirror of https://github.com/mgba-emu/mgba.git
Fill in more opcodes, implement CMN, CMP, TEQ, TST
This commit is contained in:
Jeffrey Pfau
parent
fd4ee12eb5
commit
e093960316
89
src/arm.c
89
src/arm.c
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@ -134,50 +134,43 @@ inline void ARMCycle(struct ARMCore* cpu) {
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cpu->cpsr.c = cpu->shifterCarryOut; \
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}
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// TODO: shifter
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#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, S, S_BODY, BODY, POST_BODY) \
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static void _ARMInstruction ## NAME ## S ## COND (struct ARMCore* cpu, uint32_t opcode) { \
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#define DEFINE_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, BODY) \
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static void _ARMInstruction ## NAME ## COND (struct ARMCore* cpu, uint32_t opcode) { \
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if (!COND_BODY) { \
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return; \
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} \
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BODY; \
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}
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#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, BODY) \
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DEFINE_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, BODY)
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// TODO: shifter
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#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S, S_BODY, BODY, POST_BODY) \
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DEFINE_INSTRUCTION_ARM(NAME ## S, \
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int rd = (opcode >> 12) & 0xF; \
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int rn = (opcode >> 16) & 0xF; \
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BODY; \
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S_BODY; \
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POST_BODY; \
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}
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POST_BODY;)
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#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, S, S_BODY, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, S, S_BODY, BODY, POST_BODY)
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , , BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S, S_BODY, BODY, POST_BODY)
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// Begin ALU definitions
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@ -191,6 +184,12 @@ DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cp
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DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
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int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
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int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
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@ -208,8 +207,18 @@ DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand,
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DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
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int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
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DEFINE_ALU_INSTRUCTION_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
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int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
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int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
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// End ALU definitions
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// TODO
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DEFINE_INSTRUCTION_ARM(MSR,)
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DEFINE_INSTRUCTION_ARM(MRS,)
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#define DECLARE_INSTRUCTION_ARM(COND, NAME) \
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_ARMInstruction ## NAME ## COND
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@ -253,7 +262,15 @@ DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOpe
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DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH)
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DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, TST, 0, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MSR, 0, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, TEQ, 0, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, CMP, 0, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MSR, 0, STRH, 0, 0), \
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DECLARE_ARM_ALU_BLOCK(COND, CMN, 0, LDRH, LDRSB, LDRSH)
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static const ARMInstruction armTable[0xF000] = {
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DECLARE_COND_BLOCK(EQ),
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