mirror of https://github.com/mgba-emu/mgba.git
GB: Improve emulation of DMG-on-CGB register reads
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53
src/gb/io.c
53
src/gb/io.c
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@ -99,11 +99,12 @@ static const uint8_t _registerMask[] = {
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[GB_REG_NR52] = 0x70,
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[GB_REG_STAT] = 0x80,
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[GB_REG_KEY1] = 0x7E,
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[GB_REG_VBK] = 0xFE,
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[GB_REG_VBK] = 0xFE,
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[GB_REG_OCPS] = 0x40,
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[GB_REG_BCPS] = 0x40,
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[GB_REG_OPRI] = 0xFE,
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[GB_REG_SVBK] = 0xF8,
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[GB_REG_UNK75] = 0x8F,
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[GB_REG_IE] = 0xE0,
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};
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@ -531,11 +532,8 @@ void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
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goto success;
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}
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failed:
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mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
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if (address >= GB_SIZE_IO) {
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return;
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}
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break;
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mLOG(GB_IO, GAME_ERROR, "Writing to unknown register FF%02X:%02X", address, value);
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return;
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}
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success:
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gb->memory.io[address] = value;
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@ -662,31 +660,32 @@ uint8_t GBIORead(struct GB* gb, unsigned address) {
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case GB_REG_WX:
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// Handled transparently by the registers
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break;
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default:
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if (gb->model >= GB_MODEL_CGB) {
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switch (address) {
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case GB_REG_KEY1:
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case GB_REG_VBK:
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case GB_REG_HDMA1:
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case GB_REG_HDMA2:
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case GB_REG_HDMA3:
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case GB_REG_HDMA4:
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case GB_REG_HDMA5:
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case GB_REG_BCPS:
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case GB_REG_BCPD:
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case GB_REG_OCPS:
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case GB_REG_OCPD:
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case GB_REG_SVBK:
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// Handled transparently by the registers
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goto success;
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default:
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break;
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}
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case GB_REG_KEY1:
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case GB_REG_VBK:
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case GB_REG_HDMA1:
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case GB_REG_HDMA2:
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case GB_REG_HDMA3:
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case GB_REG_HDMA4:
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case GB_REG_HDMA5:
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case GB_REG_BCPS:
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case GB_REG_BCPD:
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case GB_REG_OCPS:
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case GB_REG_OCPD:
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case GB_REG_SVBK:
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case GB_REG_UNK72:
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case GB_REG_UNK73:
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case GB_REG_UNK75:
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// Handled transparently by the registers
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if (gb->model < GB_MODEL_CGB) {
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// In DMG mode, these all get initialized to 0xFF during reset
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// But in DMG-on-CGB mode, they get initialized by the CGB reset so they can be non-zero
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mLOG(GB_IO, GAME_ERROR, "Reading from CGB register FF%02X in DMG mode", address);
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}
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break;
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default:
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mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
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return 0xFF;
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}
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success:
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return gb->memory.io[address] | _registerMask[address];
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}
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