mirror of https://github.com/mgba-emu/mgba.git
ARM: Unify barrel shifter instructions
This commit is contained in:
Vicki Pfau
parent
fff6f5890b
commit
dd053a05fe
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@ -16,21 +16,21 @@
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
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#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
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#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
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@ -9,9 +9,22 @@
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#include <mgba/internal/arm/emitter-arm.h>
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#include <mgba/internal/arm/isa-inlines.h>
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#define ADDR_MODE_1_SHIFT(OP) \
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#define ADDR_MODE_1_SHIFT \
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info->op3.reg = opcode & 0x0000000F; \
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info->op3.shifterOp = ARM_SHIFT_ ## OP; \
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switch (opcode & 0x00000060) { \
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case 0x00000000: \
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info->op3.shifterOp = ARM_SHIFT_LSL; \
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break; \
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case 0x00000020: \
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info->op3.shifterOp = ARM_SHIFT_LSR; \
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break; \
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case 0x00000040: \
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info->op3.shifterOp = ARM_SHIFT_ASR; \
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break; \
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case 0x00000060: \
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info->op3.shifterOp = ARM_SHIFT_ROR; \
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break; \
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} \
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info->operandFormat |= ARM_OPERAND_REGISTER_3; \
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if (opcode & 0x00000010) { \
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info->op3.shifterReg = (opcode >> 8) & 0xF; \
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@ -20,21 +33,14 @@
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} else { \
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info->op3.shifterImm = (opcode >> 7) & 0x1F; \
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info->operandFormat |= ARM_OPERAND_SHIFT_IMMEDIATE_3; \
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}
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#define ADDR_MODE_1_LSL \
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ADDR_MODE_1_SHIFT(LSL) \
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if (!info->op3.shifterImm) { \
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info->operandFormat &= ~ARM_OPERAND_SHIFT_IMMEDIATE_3; \
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info->op3.shifterOp = ARM_SHIFT_NONE; \
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}
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#define ADDR_MODE_1_LSR ADDR_MODE_1_SHIFT(LSR)
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#define ADDR_MODE_1_ASR ADDR_MODE_1_SHIFT(ASR)
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#define ADDR_MODE_1_ROR \
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ADDR_MODE_1_SHIFT(ROR) \
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if (!info->op3.shifterImm) { \
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info->op3.shifterOp = ARM_SHIFT_RRX; \
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if (!info->op3.shifterImm) { \
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if (info->op3.shifterOp == ARM_SHIFT_LSL) { \
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info->operandFormat &= ~ARM_OPERAND_SHIFT_IMMEDIATE_3; \
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info->op3.shifterOp = ARM_SHIFT_NONE; \
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} else if (info->op3.shifterOp == ARM_SHIFT_ROR) { \
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info->op3.shifterOp = ARM_SHIFT_RRX; \
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} \
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} \
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}
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#define ADDR_MODE_1_IMM \
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@ -114,22 +120,13 @@
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})
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#define DEFINE_ALU_DECODER_ARM(NAME, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 0, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 0, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 0, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 0, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME, NAME, 0, ADDR_MODE_1_SHIFT, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## S, NAME, 1, ADDR_MODE_1_SHIFT, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 0, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## SI, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED)
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#define DEFINE_ALU_DECODER_S_ONLY_ARM(NAME) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_NONE, 1) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_NONE, 1) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_NONE, 1) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_NONE, 1) \
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DEFINE_ALU_DECODER_EX_ARM(NAME, NAME, 1, ADDR_MODE_1_SHIFT, ARM_OPERAND_NONE, 1) \
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DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_NONE, 1)
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#define DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S, OTHER_AFFECTED) \
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@ -14,157 +14,124 @@
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#define PSR_STATE_MASK 0x00000020
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// Addressing mode 1
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static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
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static void _shift(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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++cpu->cycles;
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int shift = cpu->gprs[rs];
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if (rs == ARM_PC) {
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shift += 4;
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}
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shift &= 0xFF;
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int32_t shiftVal = cpu->gprs[rm];
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if (rm == ARM_PC) {
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shiftVal += 4;
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}
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if (!shift) {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else if (shift < 32) {
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cpu->shifterOperand = shiftVal << shift;
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cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
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} else if (shift == 32) {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = shiftVal & 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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}
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} else {
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int immediate = (opcode & 0x00000F80) >> 7;
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if (!immediate) {
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cpu->shifterOperand = cpu->gprs[rm];
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else {
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cpu->shifterOperand = cpu->gprs[rm] << immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
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}
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}
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}
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static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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++cpu->cycles;
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int shift = cpu->gprs[rs];
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int rs = (opcode >> 8) & 0x0000000F;
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uint8_t shift = cpu->gprs[rs];
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if (rs == ARM_PC) {
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shift += 4;
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}
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shift &= 0xFF;
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uint32_t shiftVal = cpu->gprs[rm];
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if (rm == ARM_PC) {
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shiftVal += 4;
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}
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if (!shift) {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else if (shift < 32) {
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cpu->shifterOperand = shiftVal >> shift;
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cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
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} else if (shift == 32) {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = shiftVal >> 31;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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}
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} else {
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int immediate = (opcode & 0x00000F80) >> 7;
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if (immediate) {
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cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
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}
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}
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}
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static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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++cpu->cycles;
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int shift = cpu->gprs[rs];
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if (rs == ARM_PC) {
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shift += 4;
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}
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shift &= 0xFF;
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int shiftVal = cpu->gprs[rm];
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if (rm == ARM_PC) {
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shiftVal += 4;
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}
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if (!shift) {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else if (shift < 32) {
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cpu->shifterOperand = shiftVal >> shift;
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cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
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} else if (cpu->gprs[rm] >> 31) {
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cpu->shifterOperand = 0xFFFFFFFF;
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cpu->shifterCarryOut = 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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return;
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}
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switch (opcode & 0x00000060) {
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// LSL
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case 0x00000000:
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if (shift < 32) {
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cpu->shifterOperand = shiftVal << shift;
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cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
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} else if (shift == 32) {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = shiftVal & 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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}
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break;
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// LSR
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case 0x00000020:
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if (shift < 32) {
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cpu->shifterOperand = shiftVal >> shift;
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cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
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} else if (shift == 32) {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = shiftVal >> 31;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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}
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break;
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// ASR
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case 0x00000040:
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if (shift < 32) {
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cpu->shifterOperand = (int32_t) shiftVal >> shift;
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cpu->shifterCarryOut = ((int32_t) shiftVal >> (shift - 1)) & 1;
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} else if (cpu->gprs[rm] >> 31) {
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cpu->shifterOperand = 0xFFFFFFFF;
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cpu->shifterCarryOut = 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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}
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break;
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// ROR
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case 0x00000060:
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{
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int rotate = shift & 0x1F;
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if (rotate) {
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cpu->shifterOperand = ROR(shiftVal, rotate);
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cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
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} else {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = ARM_SIGN(shiftVal);
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}
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}
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break;
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}
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} else {
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int immediate = (opcode & 0x00000F80) >> 7;
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if (immediate) {
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cpu->shifterOperand = cpu->gprs[rm] >> immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
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cpu->shifterOperand = cpu->shifterCarryOut;
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}
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}
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}
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static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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++cpu->cycles;
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int shift = cpu->gprs[rs];
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if (rs == ARM_PC) {
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shift += 4;
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}
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shift &= 0xFF;
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int shiftVal = cpu->gprs[rm];
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if (rm == ARM_PC) {
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shiftVal += 4;
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}
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int rotate = shift & 0x1F;
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if (!shift) {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else if (rotate) {
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cpu->shifterOperand = ROR(shiftVal, rotate);
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cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
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} else {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = ARM_SIGN(shiftVal);
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}
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} else {
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int immediate = (opcode & 0x00000F80) >> 7;
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if (immediate) {
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cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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// RRX
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cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
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cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
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switch (opcode & 0x00000060) {
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// LSL
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case 0x00000000:
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if (!immediate) {
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cpu->shifterOperand = cpu->gprs[rm];
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else {
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cpu->shifterOperand = cpu->gprs[rm] << immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
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}
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break;
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// LSR
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case 0x00000020:
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if (immediate) {
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cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
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}
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break;
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// ASR
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case 0x00000040:
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if (immediate) {
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cpu->shifterOperand = cpu->gprs[rm] >> immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
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cpu->shifterOperand = cpu->shifterCarryOut;
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}
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break;
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// ROR
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case 0x00000060:
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if (immediate) {
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cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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// RRX
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cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
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cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
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}
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break;
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}
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}
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}
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@ -318,22 +285,13 @@ ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
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})
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#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _shift, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _shift, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
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#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, _shift, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
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#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
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Loading…
Reference in New Issue