Minor cleanup

This commit is contained in:
Jeffrey Pfau 2014-01-20 18:01:49 -08:00
parent 728f6481d6
commit dccde662c6
2 changed files with 4 additions and 5 deletions

View File

@ -263,7 +263,7 @@ void GBAIOWrite(struct GBA* gba, uint32_t address, uint16_t value) {
case REG_IME: case REG_IME:
GBAWriteIME(gba, value); GBAWriteIME(gba, value);
break; break;
case 0x20A: case REG_MAX:
// Some bad interrupt libraries will write to this // Some bad interrupt libraries will write to this
break; break;
default: default:
@ -402,7 +402,7 @@ uint16_t GBAIORead(struct GBA* gba, uint32_t address) {
case REG_IME: case REG_IME:
// Handled transparently by registers // Handled transparently by registers
break; break;
case 0x20A: case REG_MAX:
// Some bad interrupt libraries will read from this // Some bad interrupt libraries will read from this
break; break;
default: default:
@ -424,7 +424,6 @@ void GBAIOSerialize(struct GBA* gba, struct GBASerializedState* state) {
} }
void GBAIODeserialize(struct GBA* gba, struct GBASerializedState* state) { void GBAIODeserialize(struct GBA* gba, struct GBASerializedState* state) {
// TODO: Actually fill this out
int i; int i;
for (i = 0; i < REG_MAX; i += 2) { for (i = 0; i < REG_MAX; i += 2) {
if (_isSpecialRegister[i >> 1]) { if (_isSpecialRegister[i >> 1]) {

View File

@ -762,9 +762,9 @@ void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* in
if (info->doIrq) { if (info->doIrq) {
info->nextIRQ = memory->p->cpu.cycles + 2; info->nextIRQ = memory->p->cpu.cycles + 2;
info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion] info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
: memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]); : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion] info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
: memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]); : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
} }
info->nextSource = source; info->nextSource = source;