diff --git a/src/arm.c b/src/arm.c
index 6a115745c..0c7ca030e 100644
--- a/src/arm.c
+++ b/src/arm.c
@@ -215,7 +215,41 @@ DEFINE_ALU_INSTRUCTION_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand
 
 // End ALU definitions
 
+// Begin multiply definitions
+
+DEFINE_INSTRUCTION_ARM(MLA,)
+DEFINE_INSTRUCTION_ARM(MLAS,)
+DEFINE_INSTRUCTION_ARM(MUL,)
+DEFINE_INSTRUCTION_ARM(MULS,)
+DEFINE_INSTRUCTION_ARM(SMLAL,)
+DEFINE_INSTRUCTION_ARM(SMLALS,)
+DEFINE_INSTRUCTION_ARM(SMULL,)
+DEFINE_INSTRUCTION_ARM(SMULLS,)
+DEFINE_INSTRUCTION_ARM(UMLAL,)
+DEFINE_INSTRUCTION_ARM(UMLALS,)
+DEFINE_INSTRUCTION_ARM(UMULL,)
+DEFINE_INSTRUCTION_ARM(UMULLS,)
+
+// End multiply definitions
+
+// Begin load/store definitions
+
+DEFINE_INSTRUCTION_ARM(LDR,)
+DEFINE_INSTRUCTION_ARM(LDRB,)
+DEFINE_INSTRUCTION_ARM(LDRH,)
+DEFINE_INSTRUCTION_ARM(LDRSB,)
+DEFINE_INSTRUCTION_ARM(LDRSH,)
+DEFINE_INSTRUCTION_ARM(STR,)
+DEFINE_INSTRUCTION_ARM(STRB,)
+DEFINE_INSTRUCTION_ARM(STRH,)
+
+DEFINE_INSTRUCTION_ARM(SWP,)
+DEFINE_INSTRUCTION_ARM(SWPB,)
+
+// End load/store definitions
+
 // TODO
+DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
 DEFINE_INSTRUCTION_ARM(MSR,)
 DEFINE_INSTRUCTION_ARM(MRS,)
 
@@ -238,39 +272,39 @@ DEFINE_INSTRUCTION_ARM(MRS,)
 #define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
 	DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
 	DECLARE_INSTRUCTION_ARM(COND, ALU), \
-	0, \
+	DECLARE_INSTRUCTION_ARM(COND, EX1), \
 	DECLARE_INSTRUCTION_ARM(COND, ALU), \
-	0, \
+	DECLARE_INSTRUCTION_ARM(COND, EX2), \
 	DECLARE_INSTRUCTION_ARM(COND, ALU), \
-	0, \
+	DECLARE_INSTRUCTION_ARM(COND, EX3), \
 	DECLARE_INSTRUCTION_ARM(COND, ALU), \
-	0
+	DECLARE_INSTRUCTION_ARM(COND, EX4)
 
 #define DECLARE_COND_BLOCK(COND) \
-	DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRH, 0, 0), \
+	DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRH, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, SUB, 0, STRH, 0, 0), \
-	DECLARE_ARM_ALU_BLOCK(COND, SUBS, 0, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, RSB, 0, STRH, 0, 0), \
-	DECLARE_ARM_ALU_BLOCK(COND, RSBS, 0, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRH, ILL, ILL), \
+	DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, STRH, ILL, ILL), \
+	DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRH, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRH, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRH, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRH, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRH, 0, 0), \
-	DECLARE_ARM_ALU_BLOCK(COND, TST, 0, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, MSR, 0, STRH, 0, 0), \
-	DECLARE_ARM_ALU_BLOCK(COND, TEQ, 0, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRH, 0, 0), \
-	DECLARE_ARM_ALU_BLOCK(COND, CMP, 0, LDRH, LDRSB, LDRSH), \
-	DECLARE_ARM_ALU_BLOCK(COND, MSR, 0, STRH, 0, 0), \
-	DECLARE_ARM_ALU_BLOCK(COND, CMN, 0, LDRH, LDRSB, LDRSH)
+	DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRH, ILL, ILL), \
+	DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRH, ILL, ILL), \
+	DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRH, ILL, ILL), \
+	DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRH, ILL, ILL), \
+	DECLARE_ARM_ALU_BLOCK(COND, CMN, ILL, LDRH, LDRSB, LDRSH)
 
 static const ARMInstruction armTable[0xF000] = {
 	DECLARE_COND_BLOCK(EQ),