From d620357ac8161a7d318b6e8909cb3d2277e658bc Mon Sep 17 00:00:00 2001 From: Jeffrey Pfau Date: Sat, 6 Apr 2013 19:52:45 -0700 Subject: [PATCH] Stub out coprocessor --- src/arm.c | 81 ++++++++++++++++++++++++++++++++----------------------- 1 file changed, 47 insertions(+), 34 deletions(-) diff --git a/src/arm.c b/src/arm.c index 98283e632..4d5deeca6 100644 --- a/src/arm.c +++ b/src/arm.c @@ -403,6 +403,10 @@ DEFINE_INSTRUCTION_ARM(MRSI,) DIRECTIVE, \ DIRECTIVE +#define DO_INTERLACE(LEFT, RIGHT) \ + LEFT, \ + RIGHT + #define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ALU) \ DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I)), \ DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I)) @@ -450,6 +454,15 @@ DEFINE_INSTRUCTION_ARM(MRSI,) DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \ DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))) +// TODO: Support coprocessors +#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, NAME, P, U, W, N) \ + DO_8(0), \ + DO_8(0) + +#define DECLARE_ARM_COPROCESSOR_BLOCK(COND, NAME1, NAME2) \ + DO_8(DO_8(DO_INTERLACE(0, 0))), \ + DO_8(DO_8(DO_INTERLACE(0, 0))) + #define DECLARE_COND_BLOCK(COND) \ DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \ DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \ @@ -627,40 +640,40 @@ DEFINE_INSTRUCTION_ARM(MRSI,) DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, W), \ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, W), \ DECLARE_ARM_BRANCH_BLOCK(COND, B), \ - DECLARE_ARM_BRANCH_BLOCK(COND, BL)//, \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \ - // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \ - // DECLARE_ARM_COPROCESSOR_BLOCK(CDP, MCR), \ + DECLARE_ARM_BRANCH_BLOCK(COND, BL), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \ + DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \ + DECLARE_ARM_COPROCESSOR_BLOCK(COND, CDP, MCR)//, \ // DECLARE_ARM_SWI_BLOCK static const ARMInstruction armTable[0x10000] = {