Python: More binding skeleton

This commit is contained in:
Jeffrey Pfau 2016-10-11 17:06:50 -07:00
parent bd7b394e49
commit d53497cb32
7 changed files with 76 additions and 3 deletions

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@ -1,6 +1,20 @@
#define COMMON_H
#define extern
#define _TIME_H_
#define _SYS_TIME_H_
#define ATTRIBUTE_FORMAT(X, Y, Z)
#define DECL_BITFIELD(newtype, oldtype) typedef oldtype newtype
#define DECL_BIT(type, name, bit)
#define DECL_BITS(type, name, bit, nbits)
typedef long time_t;
typedef ... va_list;
#include <limits.h>
#include "core/core.h"
#include "core/core.h"
#ifdef M_CORE_GBA
#include "arm/arm.h"
#include "gba/gba.h"
#endif
#ifdef M_CORE_GB
#include "lr35902/lr35902.h"
#include "gb/gb.h"
#endif

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@ -9,12 +9,22 @@ src = os.path.join(os.path.dirname(__file__), "..", "..")
ffi.set_source("mgba._pylib", """
#include "util/common.h"
#include "core/core.h"
#include "arm/arm.h"
#include "gba/gba.h"
#include "lr35902/lr35902.h"
#include "gb/gb.h"
""", include_dirs=[src],
extra_compile_args=sys.argv[1:],
libraries=["mgba"],
library_dirs=[os.path.join(os.getcwd(), "..")])
with open(os.path.join(os.getcwd(), "_builder.h")) as core:
ffi.cdef(core.read())
lines = []
for line in core:
line = line.strip()
if line.startswith('#'):
continue
lines.append(line)
ffi.cdef('\n'.join(lines))
ffi.compile()

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@ -0,0 +1,16 @@
from _pylib import ffi, lib
class _ARMRegisters:
def __init__(self, cpu):
self._cpu = cpu
def __getitem__(self, r):
if r > lib.ARM_PC:
raise IndexError("Register out of range")
return int(self._cpu._native.gprs[r])
class ARMCore:
def __init__(self, native):
self._native = ffi.cast("struct ARMCore*", native)
self.gprs = _ARMRegisters(self)

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@ -0,0 +1,5 @@
from _pylib import ffi, lib
class GB:
def __init__(self, native):
self._native = ffi.cast("struct GB*", native)

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@ -0,0 +1,5 @@
from _pylib import ffi, lib
class GBA:
def __init__(self, native):
self._native = ffi.cast("struct GBA*", native)

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@ -0,0 +1,5 @@
from _pylib import ffi, lib
class LR35902Core:
def __init__(self, native):
self._native = ffi.cast("struct LR35902*", native)

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@ -11,7 +11,15 @@ class mCore:
self._core = ffi.gc(native, self._deinit)
def init(self):
return bool(self._core.init(self._core))
success = bool(self._core.init(self._core))
if success:
if hasattr(self, 'PLATFORM_GBA') and self.platform() == self.PLATFORM_GBA:
self.cpu = ARMCore(self._core.cpu)
self.board = GBA(self._core.board)
if hasattr(self, 'PLATFORM_GB') and self.platform() == self.PLATFORM_GB:
self.cpu = LR35902Core(self._core.cpu)
self.board = GB(self._core.board)
return success
def _deinit(self):
self._core.deinit(self._core)
@ -45,3 +53,13 @@ class mCore:
def step(self):
self._core.step(self._core)
if hasattr(lib, 'PLATFORM_GBA'):
from .gba import GBA
from .arm import ARMCore
mCore.PLATFORM_GBA = lib.PLATFORM_GBA
if hasattr(lib, 'PLATFORM_GB'):
from .gb import GB
from .lr35902 import LR35902Core
mCore.PLATFORM_GB = lib.PLATFORM_GB