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GBA Memory: Simplify LDM/STM loop

This commit is contained in:
Jeffrey Pfau 2014-11-17 22:22:50 -08:00
parent 37554a40ea
commit d49df216b8
1 changed files with 34 additions and 76 deletions
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110
src/gba/gba-memory.c
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@ -668,17 +668,15 @@ void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCo
} }
} }
#define LDM_LOOP_BEGIN \ #define LDM_LOOP(LDM) \
for (i = 0; i < 16; ++i) { \ for (i = 0; i < 16; ++i) { \
if (!(mask & (1 << i))) { \ if (mask & (1 << i)) { \
continue; \ LDM; \
} waitstatesRegion = memory->waitstatesSeq32; \
cpu->gprs[i] = value; \
#define LDM_LOOP_END \ ++wait; \
waitstatesRegion = memory->waitstatesSeq32; \ address += 4; \
cpu->gprs[i] = value; \ } \
++wait; \
address += 4; \
} }
uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) { uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
@ -706,39 +704,25 @@ uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum L
switch (address >> BASE_OFFSET) { switch (address >> BASE_OFFSET) {
case REGION_BIOS: case REGION_BIOS:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_BIOS);
LOAD_BIOS;
LDM_LOOP_END;
break; break;
case REGION_WORKING_RAM: case REGION_WORKING_RAM:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_WORKING_RAM);
LOAD_WORKING_RAM;
LDM_LOOP_END;
break; break;
case REGION_WORKING_IRAM: case REGION_WORKING_IRAM:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_WORKING_IRAM);
LOAD_WORKING_IRAM;
LDM_LOOP_END;
break; break;
case REGION_IO: case REGION_IO:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_IO);
LOAD_IO;
LDM_LOOP_END;
break; break;
case REGION_PALETTE_RAM: case REGION_PALETTE_RAM:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_PALETTE_RAM);
LOAD_PALETTE_RAM;
LDM_LOOP_END;
break; break;
case REGION_VRAM: case REGION_VRAM:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_VRAM);
LOAD_VRAM;
LDM_LOOP_END;
break; break;
case REGION_OAM: case REGION_OAM:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_OAM);
LOAD_OAM;
LDM_LOOP_END;
break; break;
case REGION_CART0: case REGION_CART0:
case REGION_CART0_EX: case REGION_CART0_EX:
@ -746,20 +730,14 @@ uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum L
case REGION_CART1_EX: case REGION_CART1_EX:
case REGION_CART2: case REGION_CART2:
case REGION_CART2_EX: case REGION_CART2_EX:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_CART);
LOAD_CART;
LDM_LOOP_END;
break; break;
case REGION_CART_SRAM: case REGION_CART_SRAM:
case REGION_CART_SRAM_MIRROR: case REGION_CART_SRAM_MIRROR:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_SRAM);
LOAD_SRAM;
LDM_LOOP_END;
break; break;
default: default:
LDM_LOOP_BEGIN; LDM_LOOP(LOAD_BAD);
LOAD_BAD;
LDM_LOOP_END;
break; break;
} }
@ -778,17 +756,15 @@ uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum L
return address | addressMisalign; return address | addressMisalign;
} }
#define STM_LOOP_BEGIN \ #define STM_LOOP(STM) \
for (i = 0; i < 16; ++i) { \ for (i = 0; i < 16; ++i) { \
if (!(mask & (1 << i))) { \ if (mask & (1 << i)) { \
continue; \ value = cpu->gprs[i]; \
STM; \
waitstatesRegion = memory->waitstatesSeq32; \
++wait; \
address += 4; \
} \ } \
value = cpu->gprs[i];
#define STM_LOOP_END \
waitstatesRegion = memory->waitstatesSeq32; \
++wait; \
address += 4; \
} }
uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) { uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
@ -816,34 +792,22 @@ uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum
switch (address >> BASE_OFFSET) { switch (address >> BASE_OFFSET) {
case REGION_WORKING_RAM: case REGION_WORKING_RAM:
STM_LOOP_BEGIN; STM_LOOP(STORE_WORKING_RAM);
STORE_WORKING_RAM;
STM_LOOP_END;
break; break;
case REGION_WORKING_IRAM: case REGION_WORKING_IRAM:
STM_LOOP_BEGIN; STM_LOOP(STORE_WORKING_IRAM);
STORE_WORKING_IRAM;
STM_LOOP_END;
break; break;
case REGION_IO: case REGION_IO:
STM_LOOP_BEGIN; STM_LOOP(STORE_IO);
STORE_IO;
STM_LOOP_END;
break; break;
case REGION_PALETTE_RAM: case REGION_PALETTE_RAM:
STM_LOOP_BEGIN; STM_LOOP(STORE_PALETTE_RAM);
STORE_PALETTE_RAM;
STM_LOOP_END;
break; break;
case REGION_VRAM: case REGION_VRAM:
STM_LOOP_BEGIN; STM_LOOP(STORE_VRAM);
STORE_VRAM;
STM_LOOP_END;
break; break;
case REGION_OAM: case REGION_OAM:
STM_LOOP_BEGIN; STM_LOOP(STORE_OAM);
STORE_OAM;
STM_LOOP_END;
break; break;
case REGION_CART0: case REGION_CART0:
case REGION_CART0_EX: case REGION_CART0_EX:
@ -851,20 +815,14 @@ uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum
case REGION_CART1_EX: case REGION_CART1_EX:
case REGION_CART2: case REGION_CART2:
case REGION_CART2_EX: case REGION_CART2_EX:
STM_LOOP_BEGIN; STM_LOOP(STORE_CART);
STORE_CART;
STM_LOOP_END;
break; break;
case REGION_CART_SRAM: case REGION_CART_SRAM:
case REGION_CART_SRAM_MIRROR: case REGION_CART_SRAM_MIRROR:
STM_LOOP_BEGIN; STM_LOOP(STORE_SRAM);
STORE_SRAM;
STM_LOOP_END;
break; break;
default: default:
STM_LOOP_BEGIN; STM_LOOP(STORE_BAD);
STORE_BAD;
STM_LOOP_END;
break; break;
} }