mirror of https://github.com/mgba-emu/mgba.git
LR35902: Fill in illegal opcodes
This commit is contained in:
parent
20b2e8af7e
commit
d13e186f91
|
@ -25,6 +25,7 @@ static void GBInit(struct LR35902Core* cpu, struct LR35902Component* component);
|
|||
static void GBInterruptHandlerInit(struct LR35902InterruptHandler* irqh);
|
||||
static void GBProcessEvents(struct LR35902Core* cpu);
|
||||
static void GBSetInterrupts(struct LR35902Core* cpu, bool enable);
|
||||
static void GBIllegal(struct LR35902Core* cpu);
|
||||
static void GBHitStub(struct LR35902Core* cpu);
|
||||
|
||||
void GBCreate(struct GB* gb) {
|
||||
|
@ -124,6 +125,7 @@ void GBInterruptHandlerInit(struct LR35902InterruptHandler* irqh) {
|
|||
irqh->reset = GBReset;
|
||||
irqh->processEvents = GBProcessEvents;
|
||||
irqh->setInterrupts = GBSetInterrupts;
|
||||
irqh->hitIllegal = GBIllegal;
|
||||
irqh->hitStub = GBHitStub;
|
||||
irqh->halt = GBHalt;
|
||||
}
|
||||
|
@ -231,6 +233,11 @@ void GBHalt(struct LR35902Core* cpu) {
|
|||
cpu->halted = true;
|
||||
}
|
||||
|
||||
void GBIllegal(struct LR35902Core* cpu) {
|
||||
// TODO
|
||||
mLOG(GB, GAME_ERROR, "Hit illegal opcode at address %04X:%02X\n", cpu->pc, cpu->bus);
|
||||
}
|
||||
|
||||
void GBHitStub(struct LR35902Core* cpu) {
|
||||
// TODO
|
||||
mLOG(GB, STUB, "Hit stub at address %04X:%02X\n", cpu->pc, cpu->bus);
|
||||
|
|
|
@ -221,7 +221,7 @@
|
|||
DECLARE_INSTRUCTION_LR35902(EMITTER, RETNC), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, POPDE), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, JPNC), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, CALLNC), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, PUSHDE), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, SUB), \
|
||||
|
@ -229,32 +229,32 @@
|
|||
DECLARE_INSTRUCTION_LR35902(EMITTER, RETC), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, RETI), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, JPC), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, CALLC), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, SBC), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, RST18), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, LDIOA), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, POPHL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, LDIOCA), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, PUSHHL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, AND), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, RST20), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ADDSP), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, JPHL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, LDIA), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, XOR), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, RST28), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, LDAIO), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, POPAF), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, LDAIOC), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, DI), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, PUSHAF), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, OR), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, RST30), \
|
||||
|
@ -262,8 +262,8 @@
|
|||
DECLARE_INSTRUCTION_LR35902(EMITTER, LDSP_HL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, LDAI), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, EI), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, STUB), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, CP), \
|
||||
DECLARE_INSTRUCTION_LR35902(EMITTER, RST38)
|
||||
|
||||
|
|
|
@ -757,6 +757,7 @@ DEFINE_RST_INSTRUCTION_LR35902(28);
|
|||
DEFINE_RST_INSTRUCTION_LR35902(30);
|
||||
DEFINE_RST_INSTRUCTION_LR35902(38);
|
||||
|
||||
DEFINE_INSTRUCTION_LR35902(ILL, cpu->irqh.hitIllegal(cpu));
|
||||
DEFINE_INSTRUCTION_LR35902(STUB, cpu->irqh.hitStub(cpu));
|
||||
|
||||
static const LR35902Instruction _lr35902CBInstructionTable[0x100] = {
|
||||
|
|
|
@ -62,6 +62,7 @@ struct LR35902InterruptHandler {
|
|||
void (*setInterrupts)(struct LR35902Core* cpu, bool enable);
|
||||
void (*halt)(struct LR35902Core* cpu);
|
||||
|
||||
void (*hitIllegal)(struct LR35902Core* cpu);
|
||||
void (*hitStub)(struct LR35902Core* cpu);
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in New Issue